fold-vec-insert-char-p8.c: New.
[testsuite] 2018-10-10 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.target/powerpc/fold-vec-insert-char-p8.c: New. * gcc.target/powerpc/fold-vec-insert-char-p9.c: New. * gcc.target/powerpc/fold-vec-insert-double.c: New. * gcc.target/powerpc/fold-vec-insert-float-p8.c: New. * gcc.target/powerpc/fold-vec-insert-float-p9.c: New. * gcc.target/powerpc/fold-vec-insert-int-p8.c: New. * gcc.target/powerpc/fold-vec-insert-int-p9.c: New. * gcc.target/powerpc/fold-vec-insert-longlong.c: New. * gcc.target/powerpc/fold-vec-insert-short-p8.c: New. * gcc.target/powerpc/fold-vec-insert-short-p9.c: New. From-SVN: r265067
This commit is contained in:
Will Schmidt
Will Schmidt
parent
3c32917793
commit
47d31f1aa4
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@ -1,3 +1,16 @@
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2018-10-11 Will Schmidt <will_schmidt@vnet.ibm.com>
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* gcc.target/powerpc/fold-vec-insert-char-p8.c: New.
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* gcc.target/powerpc/fold-vec-insert-char-p9.c: New.
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* gcc.target/powerpc/fold-vec-insert-double.c: New.
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* gcc.target/powerpc/fold-vec-insert-float-p8.c: New.
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* gcc.target/powerpc/fold-vec-insert-float-p9.c: New.
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* gcc.target/powerpc/fold-vec-insert-int-p8.c: New.
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* gcc.target/powerpc/fold-vec-insert-int-p9.c: New.
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* gcc.target/powerpc/fold-vec-insert-longlong.c: New.
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* gcc.target/powerpc/fold-vec-insert-short-p8.c: New.
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* gcc.target/powerpc/fold-vec-insert-short-p9.c: New.
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2018-10-11 Will Schmidt <will_schmidt@vnet.ibm.com>
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* gcc.target/powerpc/fold-vec-extract-char.p7.c: New.
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@ -35,15 +48,6 @@
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* gcc.dg/sinatan-2.c: New test.
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* gcc.dg/sinatan-3.c: New test.
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2018-10-11 Will Schmidt <will_schmidt@vnet.ibm.com>
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* gcc.target/powerpc/fold-vec-select-char.c: New.
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* gcc.target/powerpc/fold-vec-select-double.c: New.
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* gcc.target/powerpc/fold-vec-select-float.c: New.
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* gcc.target/powerpc/fold-vec-select-int.c: New.
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* gcc.target/powerpc/fold-vec-select-longlong.c: New.
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* gcc.target/powerpc/fold-vec-select-short.c: New.
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2018-10-11 Will Schmidt <will_schmidt@vnet.ibm.com>
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* gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: New.
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@ -0,0 +1,59 @@
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/* Verify that overloaded built-ins for vec_insert () with char
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inputs produce the right codegen. */
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/* { dg-do compile { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-O2 -mcpu=power8" } */
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/* The below contains vec_insert () calls with both variable and constant
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values. Only the constant value calls are early-gimple folded, but all
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are tested for coverage. */
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#include <altivec.h>
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vector bool char testub_var (unsigned char x, vector bool char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector signed char testss_var (signed char x, vector signed char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector unsigned char testsu_var (signed char x, vector unsigned char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector unsigned char testuu_var (unsigned char x, vector unsigned char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector bool char testub_cst (unsigned char x, vector bool char v)
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{
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return vec_insert (x, v, 12);
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}
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vector signed char testss_cst (signed char x, vector signed char v)
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{
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return vec_insert (x, v, 12);
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}
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vector unsigned char testsu_cst (signed char x, vector unsigned char v)
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{
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return vec_insert (x, v, 12);
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}
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vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
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{
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return vec_insert (x, v, 12);
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}
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/* one store per _var test */
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvw4x\M} 4 } } */
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/* one store-byte per test */
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/* { dg-final { scan-assembler-times {\mstb\M} 8 } } */
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/* one load per test */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 } } */
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/* one lvebx per _cst test.*/
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/* { dg-final { scan-assembler-times {\mlvebx\M} 4 } } */
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/* one vperm per _cst test.*/
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/* { dg-final { scan-assembler-times {\mvperm\M} 4 } } */
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/* Verify that overloaded built-ins for vec_insert () with char
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inputs produce the right codegen. */
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/* { dg-do compile { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-options "-O2 -mcpu=power9" } */
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/* The below contains vec_insert () calls with both variable and constant
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values. Only the constant value calls are early-gimple folded, but all
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are tested for coverage. */
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#include <altivec.h>
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vector bool char testub_var (unsigned char x, vector bool char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector signed char testss_var (signed char x, vector signed char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector unsigned char testsu_var (signed char x, vector unsigned char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector unsigned char testuu_var (unsigned char x, vector unsigned char v, signed int i)
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{
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return vec_insert (x, v, i);
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}
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vector bool char testub_cst (unsigned char x, vector bool char v)
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{
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return vec_insert (x, v, 12);
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}
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vector signed char testss_cst (signed char x, vector signed char v)
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{
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return vec_insert (x, v, 12);
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}
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vector unsigned char testsu_cst (signed char x, vector unsigned char v)
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{
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return vec_insert (x, v, 12);
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}
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vector unsigned char testuu_cst (unsigned char x, vector unsigned char v)
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{
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return vec_insert (x, v, 12);
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}
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/* load immediate, add, store, stb, load variable test. */
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/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 4 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mlvebx\M|\mlxv\M|\mlvx\M} 4 { target lp64} } } */
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/* an insert and a move per constant test. */
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/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 4 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mvinsertb\M} 4 { target lp64 } } } */
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/* -m32 codegen. */
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/* { dg-final { scan-assembler-times {\mrlwinm\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\madd\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstxv\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mstb\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvebx\M} 4 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
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@ -0,0 +1,29 @@
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/* Verify that overloaded built-ins for vec_insert with
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double inputs produce the right codegen. */
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/* { dg-do compile { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-mvsx -O2" } */
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#include <altivec.h>
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vector double
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testd_var (double d, vector double vd, signed int si)
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{
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return vec_insert (d, vd, si);
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}
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vector double
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testd_cst (double d, vector double vd)
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{
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return vec_insert (d, vd, 1);
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}
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/* The number of xxpermdi instructions varies between
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P7,P8,P9, ensure at least one hit. */
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/* { dg-final { scan-assembler {\mxxpermdi\M} } } */
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/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstxv\M|\mstvx\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mstfdx\M|\mstfd\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 1 } } */
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/* Verify that overloaded built-ins for vec_insert with float
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inputs produce the right codegen. Power8 variant. */
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/* { dg-do compile { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-O2 -mcpu=power8" } */
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#include <altivec.h>
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vector float
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testf_var (float f, vector float vf, signed int i)
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{
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return vec_insert (f, vf, i);
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}
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vector float
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testf_cst (float f, vector float vf)
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{
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return vec_insert (f, vf, 12);
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}
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstxv\M|\mstxvd2x\M} 1 } } */
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/* cst tests has stfs instead of stfsx. */
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/* { dg-final { scan-assembler-times {\mstfs\M|\mstfsx\M} 2 } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M|\mlxvw4x\M} 2 } } */
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/* cst test has a lvewx,vperm combo */
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/* { dg-final { scan-assembler-times {\mlvewx\M} 1 } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 1 } } */
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/* Verify that overloaded built-ins for vec_insert with float
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inputs produce the right codegen. Power9 variant. */
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/* { dg-do compile { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-options "-O2 -mcpu=power9" } */
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#include <altivec.h>
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vector float
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testf_var (float f, vector float vf, signed int i)
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{
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return vec_insert (f, vf, i);
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}
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vector float
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testf_cst (float f, vector float vf)
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{
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return vec_insert (f, vf, 12);
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}
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/* var test has a load and store. */
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/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 1 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mstfsx\M} 1 { target lp64} } } */
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/* cst test have a xscvdpspn,xxextractuw,xxinsertw combo */
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/* { dg-final { scan-assembler-times {\mxscvdpspn\M} 1 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mxxextractuw\M} 1 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mxxinsertw\M} 1 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mstfs\M} 2 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlxv\M} 2 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mlvewx\M} 1 { target ilp32 } } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 1 { target ilp32 } } } */
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/* Verify that overloaded built-ins for vec_insert() with int
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inputs produce the right codegen. Power8 variant. */
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/* { dg-do compile { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-O2 -mcpu=power8" } */
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#include <altivec.h>
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vector bool int
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testbi_var(unsigned int x, vector bool int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector signed int
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testsi_var(signed int x, vector signed int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector unsigned int
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testui1_var(signed int x, vector unsigned int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector unsigned int
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testui2_var(unsigned int x, vector unsigned int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector bool int
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testbi_cst(unsigned int x, vector bool int v)
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{
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return vec_insert(x, v, 12);
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}
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vector signed int
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testsi_cst(signed int x, vector signed int v)
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{
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return vec_insert(x, v, 12);
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}
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vector unsigned int
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testui1_cst(signed int x, vector unsigned int v)
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{
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return vec_insert(x, v, 12);
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}
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vector unsigned int
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testui2_cst(unsigned int x, vector unsigned int v)
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{
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return vec_insert(x, v, 12);
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}
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/* Each test has lvx (8). cst tests have additional lvewx. (4) */
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/* var tests have both stwx (4) and stvx (4). cst tests have stw (4).*/
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/* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 12 } } */
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/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 } } */
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/* { dg-final { scan-assembler-times {\mlvewx\M} 4 } } */
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/* { dg-final { scan-assembler-times {\mvperm\M} 4 } } */
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|
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@ -0,0 +1,67 @@
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/* Verify that overloaded built-ins for vec_insert() with int
|
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inputs produce the right codegen. Power9 variant. */
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/* { dg-do compile { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-options "-O2 -mcpu=power9" } */
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#include <altivec.h>
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vector bool int
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testbi_var(unsigned int x, vector bool int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector signed int
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testsi_var(signed int x, vector signed int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector unsigned int
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testui1_var(signed int x, vector unsigned int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector unsigned int
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testui2_var(unsigned int x, vector unsigned int v, signed int i)
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{
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return vec_insert(x, v, i);
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}
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vector bool int
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testbi_cst(unsigned int x, vector bool int v)
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{
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return vec_insert(x, v, 12);
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}
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vector signed int
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testsi_cst(signed int x, vector signed int v)
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{
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return vec_insert(x, v, 12);
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}
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vector unsigned int
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testui1_cst(signed int x, vector unsigned int v)
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{
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return vec_insert(x, v, 12);
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}
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vector unsigned int
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testui2_cst(unsigned int x, vector unsigned int v)
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{
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return vec_insert(x, v, 12);
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}
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|
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/* load immediate, add, store, stb, load variable test. */
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/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 } } */
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/* { dg-final { scan-assembler-times {\mstwx\M} 4 { target lp64 } } } */
|
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/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 4 { target lp64 } } } */
|
||||
|
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/* an insert and a move per constant test. */
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/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 4 { target lp64 } } } */
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/* { dg-final { scan-assembler-times {\mxxinsertw\M} 4 { target lp64 } } } */
|
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|
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/* { dg-final { scan-assembler-times {\maddi\M} 12 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstw\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M} 8 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 { target ilp32 } } } */
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/* Verify that overloaded built-ins for vec_insert() with long long
|
||||
inputs produce the right codegen. */
|
||||
|
||||
/* { dg-do compile { target { powerpc*-*-linux* } } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-O2 -mcpu=power8" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector bool long long
|
||||
testbl_var(unsigned long long x, vector bool long long v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
|
||||
vector signed long long
|
||||
testsl_var(signed long long x, vector signed long long v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
|
||||
vector unsigned long long
|
||||
testul1_var(signed long long x, vector unsigned long long v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
|
||||
vector unsigned long long
|
||||
testul2_var(unsigned long long x, vector unsigned long long v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
|
||||
vector bool long long
|
||||
testbl_cst(unsigned long long x, vector bool long long v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
|
||||
vector signed long long
|
||||
testsl_cst(signed long long x, vector signed long long v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
|
||||
vector unsigned long long
|
||||
testul1_cst(signed long long x, vector unsigned long long v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
|
||||
vector unsigned long long
|
||||
testul2_cst(unsigned long long x, vector unsigned long long v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
|
||||
/* Number of xxpermdi insns varies between power targets. ensure at least one. */
|
||||
/* { dg-final { scan-assembler {\mxxpermdi\M} } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 4 } } */
|
||||
|
||||
/* The number of addi instructions decreases on newer systems. Measured as 8 on
|
||||
power7 and power8 targets, and drops to 4 on power9 targets that use the
|
||||
newer stxv,lxv instructions. For this test ensure we get at least one. */
|
||||
/* { dg-final { scan-assembler {\maddi\M} } } */
|
||||
/* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mstdx\M} 4 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mstw\M} 8 { target ilp32 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M|\mlvx\M} 4 } } */
|
||||
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/* Verify that overloaded built-ins for vec_insert() with short
|
||||
inputs produce the right codegen. Power8 variant. */
|
||||
|
||||
/* { dg-do compile { target { powerpc*-*-linux* } } } */
|
||||
/* { dg-require-effective-target powerpc_p8vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
|
||||
/* { dg-options "-O2 -mcpu=power8" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector bool short
|
||||
testbs_var(unsigned short x, vector bool short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector signed short
|
||||
testss_var(signed short x, vector signed short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector unsigned short
|
||||
testus1_var(signed short x, vector unsigned short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector unsigned short
|
||||
testus2_var(unsigned short x, vector unsigned short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector bool short
|
||||
testbs_cst(signed short x, vector bool short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
vector signed short
|
||||
testss_cst(signed short x, vector signed short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
vector unsigned short
|
||||
testus1_cst(signed short x, vector unsigned short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
vector unsigned short
|
||||
testus2_cst(unsigned short x, vector unsigned short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 8 } } */
|
||||
/* stores.. 2 each per variable tests, 1 each per cst test. */
|
||||
/* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 12 } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mvperm\M} 4 } } */
|
||||
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/* Verify that overloaded built-ins for vec_insert() with short
|
||||
inputs produce the right codegen. Power9 variant. */
|
||||
|
||||
/* { dg-do compile { target { powerpc*-*-linux* } } } */
|
||||
/* { dg-require-effective-target powerpc_p9vector_ok } */
|
||||
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
|
||||
/* { dg-options "-O2 -mcpu=power9" } */
|
||||
|
||||
#include <altivec.h>
|
||||
|
||||
vector bool short
|
||||
testbs_var(unsigned short x, vector bool short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector signed short
|
||||
testss_var(signed short x, vector signed short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector unsigned short
|
||||
testus1_var(signed short x, vector unsigned short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector unsigned short
|
||||
testus2_var(unsigned short x, vector unsigned short v, signed int i)
|
||||
{
|
||||
return vec_insert(x, v, i);
|
||||
}
|
||||
vector bool short
|
||||
testbs_cst(signed short x, vector bool short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
vector signed short
|
||||
testss_cst(signed short x, vector signed short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
vector unsigned short
|
||||
testus1_cst(signed short x, vector unsigned short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
vector unsigned short
|
||||
testus2_cst(unsigned short x, vector unsigned short v)
|
||||
{
|
||||
return vec_insert(x, v, 12);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mmtvsrwz\M} 4 { target lp64 } } } */
|
||||
/* { dg-final { scan-assembler-times {\mvinserth\M} 4 { target lp64 } } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times {\mstxv\M|\mstvx\M} 4 } } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 4 { target lp64 }} } */
|
||||
|
||||
/* -m32 uses sth/lvehx as part of the sequence. */
|
||||
/* { dg-final { scan-assembler-times {\msth\M} 8 { target ilp32 }} } */
|
||||
/* { dg-final { scan-assembler-times {\mlvehx\M} 4 { target ilp32 }} } */
|
||||
/* { dg-final { scan-assembler-times {\mlxv\M|\mlvx\M} 8 { target ilp32 }} } */
|
||||
|
||||
Loading…
Reference in New Issue