arm.c (arm_address_offset_is_imm): New.
* config/arm/arm.c (arm_address_offset_is_imm): New. (arm_early_store_addr_dep): New. (arm_early_load_addr_dep): New. * config/arm/arm-protos.h (arm_early_store_addr_dep): Declare. (arm_early_load_addr_dep): Declare. (arm_address_offset_is_imm): Declare. * config/arm/cortex-m4.md: New file. * config/arm/cortex-m4-fpu.md: New file. * config/arm/arm.md: Include cortex-m4.md and cortex-m4-fpu.md. (attr generic_sched): Exclude cortexm4. (attr generic_vfp): Exclude cortexm4. From-SVN: r164440
This commit is contained in:
Jie Zhang
Jie Zhang
parent
06baaba377
commit
47d8f18da2
@ -1,3 +1,17 @@
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2010-09-20 Jie Zhang <jie@codesourcery.com>
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* config/arm/arm.c (arm_address_offset_is_imm): New.
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(arm_early_store_addr_dep): New.
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(arm_early_load_addr_dep): New.
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* config/arm/arm-protos.h (arm_early_store_addr_dep): Declare.
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(arm_early_load_addr_dep): Declare.
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(arm_address_offset_is_imm): Declare.
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* config/arm/cortex-m4.md: New file.
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* config/arm/cortex-m4-fpu.md: New file.
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* config/arm/arm.md: Include cortex-m4.md and cortex-m4-fpu.md.
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(attr generic_sched): Exclude cortexm4.
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(attr generic_vfp): Exclude cortexm4.
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2010-09-20 Richard Guenther <rguenther@suse.de>
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PR middle-end/45704
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@ -86,6 +86,8 @@ extern int arm_coproc_mem_operand (rtx, bool);
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extern int neon_vector_mem_operand (rtx, int);
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extern int neon_struct_mem_operand (rtx);
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extern int arm_no_early_store_addr_dep (rtx, rtx);
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extern int arm_early_store_addr_dep (rtx, rtx);
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extern int arm_early_load_addr_dep (rtx, rtx);
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extern int arm_no_early_alu_shift_dep (rtx, rtx);
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extern int arm_no_early_alu_shift_value_dep (rtx, rtx);
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extern int arm_no_early_mul_dep (rtx, rtx);
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@ -127,6 +129,7 @@ extern const char *output_move_quad (rtx *);
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extern const char *output_move_vfp (rtx *operands);
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extern const char *output_move_neon (rtx *operands);
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extern int arm_attr_length_move_neon (rtx);
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extern int arm_address_offset_is_imm (rtx);
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extern const char *output_add_immediate (rtx *);
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extern const char *arithmetic_instr (rtx, int);
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extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int);
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@ -13345,6 +13345,34 @@ arm_attr_length_move_neon (rtx insn)
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return 4;
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}
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/* Return nonzero if the offset in the address is an immediate. Otherwise,
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return zero. */
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int
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arm_address_offset_is_imm (rtx insn)
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{
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rtx mem, addr;
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extract_insn_cached (insn);
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if (REG_P (recog_data.operand[0]))
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return 0;
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mem = recog_data.operand[0];
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gcc_assert (MEM_P (mem));
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addr = XEXP (mem, 0);
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if (GET_CODE (addr) == REG
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|| (GET_CODE (addr) == PLUS
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&& GET_CODE (XEXP (addr, 0)) == REG
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&& GET_CODE (XEXP (addr, 1)) == CONST_INT))
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return 1;
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else
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return 0;
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}
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/* Output an ADD r, s, #n where n may be too big for one instruction.
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If adding zero to one register, output nothing. */
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const char *
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@ -21503,6 +21531,38 @@ arm_no_early_store_addr_dep (rtx producer, rtx consumer)
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return !reg_overlap_mentioned_p (value, addr);
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}
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/* Return nonzero if the CONSUMER instruction (a store) does need
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PRODUCER's value to calculate the address. */
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int
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arm_early_store_addr_dep (rtx producer, rtx consumer)
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{
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return !arm_no_early_store_addr_dep (producer, consumer);
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}
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/* Return nonzero if the CONSUMER instruction (a load) does need
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PRODUCER's value to calculate the address. */
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int
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arm_early_load_addr_dep (rtx producer, rtx consumer)
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{
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rtx value = PATTERN (producer);
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rtx addr = PATTERN (consumer);
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if (GET_CODE (value) == COND_EXEC)
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value = COND_EXEC_CODE (value);
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if (GET_CODE (value) == PARALLEL)
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value = XVECEXP (value, 0, 0);
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value = XEXP (value, 0);
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if (GET_CODE (addr) == COND_EXEC)
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addr = COND_EXEC_CODE (addr);
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if (GET_CODE (addr) == PARALLEL)
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addr = XVECEXP (addr, 0, 0);
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addr = XEXP (addr, 1);
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return reg_overlap_mentioned_p (value, addr);
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}
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/* Return nonzero if the CONSUMER instruction (an ALU op) does not
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have an early register shift value or amount dependency on the
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result of PRODUCER. */
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@ -497,16 +497,16 @@
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;; True if the generic scheduling description should be used.
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(define_attr "generic_sched" "yes,no"
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(const (if_then_else
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(ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
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(eq_attr "tune_cortexr4" "yes"))
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(const (if_then_else
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(ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9,cortexm4")
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(eq_attr "tune_cortexr4" "yes"))
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(const_string "no")
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(const_string "yes"))))
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(define_attr "generic_vfp" "yes,no"
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(const (if_then_else
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(and (eq_attr "fpu" "vfp")
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(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
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(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9,cortexm4")
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(eq_attr "tune_cortexr4" "no"))
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(const_string "yes")
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(const_string "no"))))
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@ -521,6 +521,8 @@
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(include "cortex-a9.md")
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(include "cortex-r4.md")
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(include "cortex-r4f.md")
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(include "cortex-m4.md")
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(include "cortex-m4-fpu.md")
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(include "vfp11.md")
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111
gcc/config/arm/cortex-m4-fpu.md
Normal file
111
gcc/config/arm/cortex-m4-fpu.md
Normal file
@ -0,0 +1,111 @@
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;; ARM Cortex-M4 FPU pipeline description
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;; Copyright (C) 2010 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Use an artifial unit to model FPU.
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(define_cpu_unit "cortex_m4_v" "cortex_m4")
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(define_reservation "cortex_m4_ex_v" "cortex_m4_ex+cortex_m4_v")
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;; Integer instructions following VDIV or VSQRT complete out-of-order.
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(define_insn_reservation "cortex_m4_fdivs" 15
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fdivs"))
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"cortex_m4_ex_v,cortex_m4_v*13")
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(define_insn_reservation "cortex_m4_vmov_1" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fcpys,fconsts"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_vmov_2" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_2_r,r_2_f"))
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"cortex_m4_ex_v*2")
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(define_insn_reservation "cortex_m4_fmuls" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fmuls"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_fmacs" 4
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fmacs"))
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"cortex_m4_ex_v*3")
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(define_insn_reservation "cortex_m4_ffariths" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "ffariths"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_fadds" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fadds"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_fcmps" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "fcmps"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_f_flag" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_flag"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_f_cvt" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_cvt"))
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"cortex_m4_ex_v")
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(define_insn_reservation "cortex_m4_f_load" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_load"))
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"cortex_m4_ex_v*2")
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(define_insn_reservation "cortex_m4_f_store" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_store"))
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"cortex_m4_ex_v*2")
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(define_insn_reservation "cortex_m4_f_loadd" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_loadd"))
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"cortex_m4_ex_v*3")
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(define_insn_reservation "cortex_m4_f_stored" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "f_stored"))
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"cortex_m4_ex_v*3")
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;; MAC instructions consume their addend one cycle later. If the result
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;; of an arithmetic instruction is consumed as the addend of the following
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;; MAC instruction, the latency can be decreased by one.
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(define_bypass 1 "cortex_m4_fadds,cortex_m4_fmuls,cortex_m4_f_cvt"
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"cortex_m4_fmacs"
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"arm_no_early_mul_dep")
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(define_bypass 3 "cortex_m4_fmacs"
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"cortex_m4_fmacs"
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"arm_no_early_mul_dep")
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(define_bypass 14 "cortex_m4_fdivs"
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"cortex_m4_fmacs"
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"arm_no_early_mul_dep")
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111
gcc/config/arm/cortex-m4.md
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111
gcc/config/arm/cortex-m4.md
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@ -0,0 +1,111 @@
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;; ARM Cortex-M4 pipeline description
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;; Copyright (C) 2010 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "cortex_m4")
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;; We model the pipelining of LDR instructions by using two artificial units.
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(define_cpu_unit "cortex_m4_a" "cortex_m4")
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(define_cpu_unit "cortex_m4_b" "cortex_m4")
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(define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
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;; ALU and multiply is one cycle.
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(define_insn_reservation "cortex_m4_alu" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "alu,alu_shift,alu_shift_reg,mult"))
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"cortex_m4_ex")
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;; Byte, half-word and word load is two cycles.
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(define_insn_reservation "cortex_m4_load1" 2
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load_byte,load1"))
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"cortex_m4_a, cortex_m4_b")
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;; str rx, [ry, #imm] is always one cycle.
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(define_insn_reservation "cortex_m4_store1_1" 1
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(and (and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store1"))
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(ne (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
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"cortex_m4_a")
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;; Other byte, half-word and word load is two cycles.
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(define_insn_reservation "cortex_m4_store1_2" 2
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(and (and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store1"))
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(eq (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
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"cortex_m4_a*2")
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(define_insn_reservation "cortex_m4_load2" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load2"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_store2" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store2"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_load3" 4
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load3"))
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"cortex_m4_ex*4")
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(define_insn_reservation "cortex_m4_store3" 4
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store3"))
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"cortex_m4_ex*4")
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(define_insn_reservation "cortex_m4_load4" 5
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "load4"))
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"cortex_m4_ex*5")
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(define_insn_reservation "cortex_m4_store4" 5
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "store4"))
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"cortex_m4_ex*5")
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;; If the address of load or store depends on the result of the preceding
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;; instruction, the latency is increased by one.
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(define_bypass 2 "cortex_m4_alu"
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"cortex_m4_load1"
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"arm_early_load_addr_dep")
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(define_bypass 2 "cortex_m4_alu"
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"cortex_m4_store1_1,cortex_m4_store1_2"
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"arm_early_store_addr_dep")
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(define_insn_reservation "cortex_m4_branch" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "branch"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_call" 3
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "call"))
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"cortex_m4_ex*3")
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(define_insn_reservation "cortex_m4_block" 1
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(and (eq_attr "tune" "cortexm4")
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(eq_attr "type" "block"))
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"cortex_m4_ex")
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