c4x.c (c4x_emit_move_sequence): Do not force large constants into memory.
Sat Sep 4 11:37:15 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz> * config/c4x/c4x.c (c4x_emit_move_sequence): Do not force large constants into memory. (c4x_shiftable_constant): New function. * config/c4x/c4x.c (LEGITIMATE_CONSTANT_P): Allow any CONST_INT. (c4x_shiftable_constant): Declare. * config/c4x/c4x.md (loadqi_big_constant, loadhi_big_constant, ashlqi3_noclobber): Add new patterns and associated splitters. From-SVN: r29092
This commit is contained in:
Michael Hayes
Michael Hayes
parent
3de900268e
commit
483dd5bec1
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@ -1,3 +1,13 @@
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Sat Sep 4 11:37:15 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.c (c4x_emit_move_sequence): Do not force large
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constants into memory.
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(c4x_shiftable_constant): New function.
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* config/c4x/c4x.c (LEGITIMATE_CONSTANT_P): Allow any CONST_INT.
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(c4x_shiftable_constant): Declare.
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* config/c4x/c4x.md (loadqi_big_constant, loadhi_big_constant,
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ashlqi3_noclobber): Add new patterns and associated splitters.
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Fri Sep 3 16:22:17 1999 Richard Henderson <rth@cygnus.com>
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* dbxout.c (dbxout_init): Use xcalloc instead of xmalloc+bzero.
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@ -1074,20 +1074,6 @@ c4x_emit_move_sequence (operands, mode)
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constants... */
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op1 = force_const_mem (mode, op1);
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}
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else if (mode == QImode && CONSTANT_P (op1) && ! LEGITIMATE_CONSTANT_P (op1))
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{
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/* We shouldn't need this test if only emit_move_insn was called.
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However, some routines call gen_move_insn which doesn't check that
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the constants are legitimate. */
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op1 = force_const_mem (mode, op1);
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}
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else if (mode == HImode && CONSTANT_P (op1) && ! LEGITIMATE_CONSTANT_P (op1))
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{
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/* We could load all sorts of constants in two goes by pulling all
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sorts of tricks... The tricky thing is that we cannot clobber CC
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so that stifles most of the obvious methods. */
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op1 = force_const_mem (mode, op1);
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}
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/* Convert (MEM (SYMREF)) to a (MEM (LO_SUM (REG) (SYMREF)))
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and emit associated (HIGH (SYMREF)) if large memory model.
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@ -2258,6 +2244,27 @@ c4x_immed_float_constant (op)
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}
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int
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c4x_shiftable_constant (op)
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rtx op;
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{
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int i;
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int mask;
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int val = INTVAL (op);
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for (i = 0; i < 16; i++)
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{
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if (val & (1 << i))
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break;
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}
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mask = ((0xffff >> i) << 16) | 0xffff;
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if (IS_INT16_CONST (val & 0x80000000 ? (val >> i) | ~mask
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: (val >> i) & mask))
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return i;
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return -1;
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}
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int
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c4x_H_constant (op)
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rtx op;
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@ -2760,7 +2767,7 @@ reg_operand (op, mode)
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int
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mixed_subreg_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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/* Allow (subreg:HF (reg:HI)) that be generated for a union of an
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int and a long double. */
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@ -1675,7 +1675,7 @@ extern struct rtx_def *c4x_legitimize_reload_address ();
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#define LEGITIMATE_CONSTANT_P(X) \
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((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
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|| (GET_CODE (X) == CONST_INT && c4x_I_constant (X)) \
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|| (GET_CODE (X) == CONST_INT) \
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|| (GET_CODE (X) == SYMBOL_REF) \
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|| (GET_CODE (X) == LABEL_REF) \
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|| (GET_CODE (X) == CONST) \
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@ -2750,6 +2750,8 @@ extern int not_rc_reg ();
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extern int not_modify_reg ();
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extern int c4x_shiftable_constant ();
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extern int c4x_H_constant ();
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extern int c4x_I_constant ();
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@ -1130,11 +1130,13 @@
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"")
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(define_split
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[(set (match_operand:QI 0 "std_reg_operand" "")
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[(set (match_operand:QI 0 "reg_operand" "")
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(match_operand:QI 1 "const_int_operand" ""))]
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"! TARGET_C3X
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&& (INTVAL (operands[1]) & ~0xffff) != 0
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&& (INTVAL (operands[1]) & 0xffff) != 0"
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&& ! IS_INT16_CONST (INTVAL (operands[1]))
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&& ! IS_HIGH_CONST (INTVAL (operands[1]))
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&& reload_completed
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&& std_reg_operand (operands[0], QImode)"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
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"
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@ -1143,6 +1145,104 @@
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operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
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}")
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(define_split
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[(set (match_operand:QI 0 "reg_operand" "")
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(match_operand:QI 1 "const_int_operand" ""))]
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"TARGET_C3X && ! TARGET_SMALL
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&& ! IS_INT16_CONST (INTVAL (operands[1]))
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&& reload_completed
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&& std_reg_operand (operands[0], QImode)
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&& c4x_shiftable_constant (operands[1]) < 0"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 4)))
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(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 3)))]
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"
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{
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/* Generate two's complement value of 16 MSBs. */
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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(((INTVAL (operands[1]) >> 16) & 0xffff)
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- 0x8000) ^ ~0x7fff);
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operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
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operands[4] = gen_rtx (CONST_INT, VOIDmode, 16);
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}")
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(define_split
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[(set (match_operand:QI 0 "reg_operand" "")
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(match_operand:QI 1 "const_int_operand" ""))]
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"TARGET_C3X
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&& ! IS_INT16_CONST (INTVAL (operands[1]))
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&& reload_completed
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&& std_reg_operand (operands[0], QImode)
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&& c4x_shiftable_constant (operands[1]) >= 0"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0) (ashift:QI (match_dup 0) (match_dup 3)))]
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"
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{
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/* Generate two's complement value of MSBs. */
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int shift = c4x_shiftable_constant (operands[1]);
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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(((INTVAL (operands[1]) >> shift) & 0xffff)
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- 0x8000) ^ ~0x7fff);
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operands[3] = gen_rtx (CONST_INT, VOIDmode, shift);
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}")
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(define_split
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[(set (match_operand:QI 0 "reg_operand" "")
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(match_operand:QI 1 "const_int_operand" ""))]
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"! TARGET_SMALL
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&& ! IS_INT16_CONST (INTVAL (operands[1]))
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&& ! IS_HIGH_CONST (INTVAL (operands[1]))
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&& reload_completed
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&& ! std_reg_operand (operands[0], QImode)"
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[(set (match_dup 2) (high:QI (match_dup 3)))
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(set (match_dup 0) (match_dup 4))
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(use (match_dup 1))]
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"
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{
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rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
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operands[2] = dp_reg;
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operands[3] = force_const_mem (Pmode, operands[1]);
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operands[4] = change_address (operands[3], QImode,
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gen_rtx_LO_SUM (Pmode, dp_reg,
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XEXP (operands[3], 0)));
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operands[3] = XEXP (operands[3], 0);
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}")
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(define_split
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[(set (match_operand:QI 0 "reg_operand" "")
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(match_operand:QI 1 "const_int_operand" ""))]
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"TARGET_SMALL
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&& ! IS_INT16_CONST (INTVAL (operands[1]))
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&& ! IS_HIGH_CONST (INTVAL (operands[1]))
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&& reload_completed
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&& (TARGET_C3X && c4x_shiftable_constant (operands[1]) < 0
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|| ! std_reg_operand (operands[0], QImode))"
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[(set (match_dup 0) (match_dup 2))
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(use (match_dup 1))]
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"
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{
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rtx dp_reg = gen_rtx_REG (Pmode, DP_REGNO);
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operands[2] = force_const_mem (Pmode, operands[1]);
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operands[2] = change_address (operands[2], QImode,
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gen_rtx_LO_SUM (Pmode, dp_reg,
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XEXP (operands[2], 0)));
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}")
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(define_split
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[(set (match_operand:HI 0 "reg_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))]
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"reload_completed"
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[(set (match_dup 2) (match_dup 4))
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(set (match_dup 3) (match_dup 5))]
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"
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{
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operands[2] = c4x_operand_subword (operands[0], 0, 1, HImode);
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operands[3] = c4x_operand_subword (operands[0], 1, 1, HImode);
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operands[4] = c4x_operand_subword (operands[1], 0, 1, HImode);
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operands[5] = c4x_operand_subword (operands[1], 1, 1, HImode);
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}")
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; CC has been selected to load a symbolic address. We force the address
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; into memory and then generate LDP and LDIU insns.
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; This is also required for the C30 if we pretend that we can
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@ -1189,7 +1289,14 @@
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(define_insn "load_immed_address"
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[(set (match_operand:QI 0 "reg_operand" "=a?x?c*r")
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(match_operand:QI 1 "symbolic_address_operand" ""))]
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"TARGET_LOAD_ADDRESS"
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"TARGET_LOAD_ADDRESS"
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"#"
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[(set_attr "type" "multi")])
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(define_insn "loadhi_big_constant"
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[(set (match_operand:HI 0 "reg_operand" "=c*d")
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(match_operand:HI 1 "const_int_operand" ""))]
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""
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"#"
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[(set_attr "type" "multi")])
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@ -1207,6 +1314,14 @@
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"stik\\t%1,%0"
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[(set_attr "type" "store")])
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(define_insn "loadqi_big_constant"
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[(set (match_operand:QI 0 "reg_operand" "=c*d")
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(match_operand:QI 1 "const_int_operand" ""))]
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"! IS_INT16_CONST (INTVAL (operands[1]))
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&& ! IS_HIGH_CONST (INTVAL (operands[1]))"
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"#"
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[(set_attr "type" "multi")])
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; We must provide an alternative to store to memory in case we have to
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; spill a register.
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(define_insn "movqi_noclobber"
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@ -2516,6 +2631,19 @@
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[(set_attr "type" "binarycc,binarycc,binarycc")])
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; Default to int16 data attr.
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(define_insn "ashlqi3_noclobber"
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[(set (match_operand:QI 0 "std_reg_operand" "=c,c,?c")
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(ashift:QI (match_operand:QI 1 "src_operand" "0,rR,rS<>")
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(match_operand:QI 2 "src_operand" "rIm,JR,rS<>")))]
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"valid_operands (ASHIFT, operands, QImode)"
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"@
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ash\\t%2,%0
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ash3\\t%2,%1,%0
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ash3\\t%2,%1,%0"
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[(set_attr "type" "binary,binary,binary")])
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; Default to int16 data attr.
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; This is only used by lshrhi3_reg where we need a LSH insn that will
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; shift both ways.
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(define_insn "*lshlqi3_clobber"
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