(strict_single_insn_op_p, relop): Deleted these useless functions.
From-SVN: r1409
This commit is contained in:
Richard Stallman
parent
079a79484f
commit
483f4fb305
@ -1,495 +1,3 @@
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/* Subroutines for insn-output.c for Intel 860
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Copyright (C) 1989, 1991 Free Software Foundation, Inc.
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Derived from sparc.c.
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Written by Richard Stallman (rms@ai.mit.edu).
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Hacked substantially by Ron Guilmette (rfg@ncd.com) to cater
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to the whims of the System V Release 4 assembler.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "config.h"
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#include "flags.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "recog.h"
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#include "insn-attr.h"
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#include <stdio.h>
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static rtx find_addr_reg ();
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#ifndef I860_REG_PREFIX
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#define I860_REG_PREFIX ""
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#endif
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char *i860_reg_prefix = I860_REG_PREFIX;
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/* Save information from a "cmpxx" operation until the branch is emitted. */
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rtx i860_compare_op0, i860_compare_op1;
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/* Return non-zero if this pattern, can be evaluated safely, even if it
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was not asked for. */
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int
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safe_insn_src_p (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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/* Just experimenting. */
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/* No floating point src is safe if it contains an arithmetic
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operation, since that operation may trap. */
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switch (GET_CODE (op))
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{
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case CONST_INT:
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case LABEL_REF:
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case SYMBOL_REF:
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case CONST:
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return 1;
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case REG:
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return 1;
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case MEM:
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return CONSTANT_ADDRESS_P (XEXP (op, 0));
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/* We never need to negate or complement constants. */
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case NEG:
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return (mode != SFmode && mode != DFmode);
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case NOT:
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case ZERO_EXTEND:
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return 1;
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case EQ:
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case NE:
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case LT:
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case GT:
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case LE:
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case GE:
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case LTU:
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case GTU:
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case LEU:
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case GEU:
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case MINUS:
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case PLUS:
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return (mode != SFmode && mode != DFmode);
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case AND:
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case IOR:
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case XOR:
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case LSHIFT:
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case ASHIFT:
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case ASHIFTRT:
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case LSHIFTRT:
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if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0)))
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|| (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1))))
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return 0;
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return 1;
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default:
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return 0;
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}
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}
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/* Return 1 if REG is clobbered in IN.
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Return 2 if REG is used in IN.
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Return 3 if REG is both used and clobbered in IN.
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Return 0 if neither. */
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static int
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reg_clobbered_p (reg, in)
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rtx reg;
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rtx in;
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{
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register enum rtx_code code;
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if (in == 0)
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return 0;
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code = GET_CODE (in);
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if (code == SET || code == CLOBBER)
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{
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rtx dest = SET_DEST (in);
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int set = 0;
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int used = 0;
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while (GET_CODE (dest) == STRICT_LOW_PART
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|| GET_CODE (dest) == SUBREG
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|| GET_CODE (dest) == SIGN_EXTRACT
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|| GET_CODE (dest) == ZERO_EXTRACT)
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dest = XEXP (dest, 0);
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if (dest == reg)
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set = 1;
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else if (GET_CODE (dest) == REG
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&& refers_to_regno_p (REGNO (reg),
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REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
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SET_DEST (in), 0))
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{
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set = 1;
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/* Anything that sets just part of the register
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is considered using as well as setting it.
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But note that a straight SUBREG of a single-word value
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clobbers the entire value. */
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if (dest != SET_DEST (in)
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&& ! (GET_CODE (SET_DEST (in)) == SUBREG
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|| UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
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used = 1;
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}
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if (code == SET)
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{
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if (set)
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used = refers_to_regno_p (REGNO (reg),
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REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
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SET_SRC (in), 0);
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else
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used = refers_to_regno_p (REGNO (reg),
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REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
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in, 0);
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}
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return set + used * 2;
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}
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if (refers_to_regno_p (REGNO (reg),
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REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
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in, 0))
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return 2;
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return 0;
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}
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/* Return non-zero if OP can be written to without screwing up
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GCC's model of what's going on. It is assumed that this operand
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appears in the dest position of a SET insn in a conditional
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branch's delay slot. AFTER is the label to start looking from. */
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int
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operand_clobbered_before_used_after (op, after)
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rtx op;
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rtx after;
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{
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/* Just experimenting. */
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if (GET_CODE (op) == CC0)
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return 1;
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if (GET_CODE (op) == REG)
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{
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rtx insn;
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if (op == stack_pointer_rtx)
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return 0;
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/* Scan forward from the label, to see if the value of OP
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is clobbered before the first use. */
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for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn))
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{
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if (GET_CODE (insn) == NOTE)
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continue;
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if (GET_CODE (insn) == INSN
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|| GET_CODE (insn) == JUMP_INSN
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|| GET_CODE (insn) == CALL_INSN)
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{
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switch (reg_clobbered_p (op, PATTERN (insn)))
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{
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default:
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return 0;
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case 1:
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return 1;
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case 0:
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break;
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}
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}
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/* If we reach another label without clobbering OP,
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then we cannot safely write it here. */
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else if (GET_CODE (insn) == CODE_LABEL)
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return 0;
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if (GET_CODE (insn) == JUMP_INSN)
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{
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if (condjump_p (insn))
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return 0;
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/* This is a jump insn which has already
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been mangled. We can't tell what it does. */
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if (GET_CODE (PATTERN (insn)) == PARALLEL)
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return 0;
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if (! JUMP_LABEL (insn))
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return 0;
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/* Keep following jumps. */
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insn = JUMP_LABEL (insn);
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}
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}
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return 1;
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}
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/* In both of these cases, the first insn executed
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for this op will be a orh whatever%h,%?r0,%?r31,
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which is tolerable. */
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if (GET_CODE (op) == MEM)
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return (CONSTANT_ADDRESS_P (XEXP (op, 0)));
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return 0;
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}
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/* Return non-zero if this pattern, as a source to a "SET",
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is known to yield an instruction of unit size. */
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int
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single_insn_src_p (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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switch (GET_CODE (op))
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{
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case CONST_INT:
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/* This is not always a single insn src, technically,
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but output_delayed_branch knows how to deal with it. */
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return 1;
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case SYMBOL_REF:
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case CONST:
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/* This is not a single insn src, technically,
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but output_delayed_branch knows how to deal with it. */
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return 1;
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case REG:
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return 1;
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case MEM:
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return 1;
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/* We never need to negate or complement constants. */
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case NEG:
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return (mode != DFmode);
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case NOT:
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case ZERO_EXTEND:
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return 1;
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case PLUS:
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case MINUS:
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/* Detect cases that require multiple instructions. */
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if (CONSTANT_P (XEXP (op, 1))
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&& !(GET_CODE (XEXP (op, 1)) == CONST_INT
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&& SMALL_INT (XEXP (op, 1))))
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return 0;
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case EQ:
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case NE:
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case LT:
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case GT:
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case LE:
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case GE:
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case LTU:
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case GTU:
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case LEU:
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case GEU:
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/* Not doing floating point, since they probably
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take longer than the branch slot they might fill. */
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return (mode != SFmode && mode != DFmode);
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case AND:
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if (GET_CODE (XEXP (op, 1)) == NOT)
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{
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rtx arg = XEXP (XEXP (op, 1), 0);
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if (CONSTANT_P (arg)
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&& !(GET_CODE (arg) == CONST_INT
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&& (SMALL_INT (arg)
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|| INTVAL (arg) & 0xffff == 0)))
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return 0;
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}
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case IOR:
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case XOR:
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/* Both small and round numbers take one instruction;
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others take two. */
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if (CONSTANT_P (XEXP (op, 1))
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&& !(GET_CODE (XEXP (op, 1)) == CONST_INT
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&& (SMALL_INT (XEXP (op, 1))
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|| INTVAL (XEXP (op, 1)) & 0xffff == 0)))
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return 0;
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case LSHIFT:
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case ASHIFT:
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case ASHIFTRT:
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case LSHIFTRT:
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return 1;
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case SUBREG:
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if (SUBREG_WORD (op) != 0)
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return 0;
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return single_insn_src_p (SUBREG_REG (op), mode);
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/* Not doing floating point, since they probably
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take longer than the branch slot they might fill. */
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case FLOAT_EXTEND:
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case FLOAT_TRUNCATE:
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case FLOAT:
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case FIX:
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case UNSIGNED_FLOAT:
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case UNSIGNED_FIX:
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return 0;
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default:
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return 0;
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}
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}
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/* Nonzero only if this *really* is a single insn operand. */
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int
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strict_single_insn_op_p (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (mode == VOIDmode)
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mode = GET_MODE (op);
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switch (GET_CODE (op))
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{
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case CC0:
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return 1;
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case CONST_INT:
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if (SMALL_INT (op))
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return 1;
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/* We can put this set insn into delay slot, because this is one
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insn; `orh'. */
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if ((INTVAL (op) & 0xffff) == 0)
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return 1;
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return 0;
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case SYMBOL_REF:
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return 0;
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case REG:
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#if 0
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/* This loses when moving an freg to a general reg. */
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return HARD_REGNO_NREGS (REGNO (op), mode) == 1;
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#endif
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return (mode != DFmode && mode != DImode);
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case MEM:
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if (! CONSTANT_ADDRESS_P (XEXP (op, 0)))
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return (mode != DFmode && mode != DImode);
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return 0;
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/* We never need to negate or complement constants. */
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case NEG:
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return (mode != DFmode);
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case NOT:
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case ZERO_EXTEND:
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return 1;
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case PLUS:
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case MINUS:
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/* Detect cases that require multiple instructions. */
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if (CONSTANT_P (XEXP (op, 1))
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&& !(GET_CODE (XEXP (op, 1)) == CONST_INT
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&& SMALL_INT (XEXP (op, 1))))
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return 0;
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case EQ:
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case NE:
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case LT:
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case GT:
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case LE:
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case GE:
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case LTU:
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case GTU:
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case LEU:
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case GEU:
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return 1;
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case AND:
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if (GET_CODE (XEXP (op, 1)) == NOT)
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{
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rtx arg = XEXP (XEXP (op, 1), 0);
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if (CONSTANT_P (arg)
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&& !(GET_CODE (arg) == CONST_INT
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&& (SMALL_INT (arg)
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|| INTVAL (arg) & 0xffff == 0)))
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return 0;
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}
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case IOR:
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case XOR:
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/* Both small and round numbers take one instruction;
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others take two. */
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if (CONSTANT_P (XEXP (op, 1))
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&& !(GET_CODE (XEXP (op, 1)) == CONST_INT
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&& (SMALL_INT (XEXP (op, 1))
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|| INTVAL (XEXP (op, 1)) & 0xffff == 0)))
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return 0;
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case LSHIFT:
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case ASHIFT:
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case ASHIFTRT:
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case LSHIFTRT:
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return 1;
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case SUBREG:
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if (SUBREG_WORD (op) != 0)
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return 0;
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return strict_single_insn_op_p (SUBREG_REG (op), mode);
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case SIGN_EXTEND:
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if (GET_CODE (XEXP (op, 0)) == MEM
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&& ! CONSTANT_ADDRESS_P (XEXP (XEXP (op, 0), 0)))
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return 1;
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return 0;
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/* Not doing floating point, since they probably
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take longer than the branch slot they might fill. */
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case FLOAT_EXTEND:
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case FLOAT_TRUNCATE:
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case FLOAT:
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case FIX:
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case UNSIGNED_FLOAT:
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case UNSIGNED_FIX:
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return 0;
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default:
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return 0;
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}
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}
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/* Return truth value of whether OP is a relational operator. */
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int
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relop (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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switch (GET_CODE (op))
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{
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case EQ:
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case NE:
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case GT:
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case GE:
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case LT:
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case LE:
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case GTU:
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case GEU:
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case LTU:
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case LEU:
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return 1;
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}
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return 0;
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}
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/* Return non-zero only if OP is a register of mode MODE,
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or const0_rtx. */
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@ -1691,7 +1199,7 @@ sfmode_constant_to_ulong (x)
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for saving all of the "preserved" registers (and use that number, i.e.
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`80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
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the lower part of the frame. That could potentially be very wasteful,
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and that wastefulness could really hamper people compiling for embedded
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and that could cause serious problems when compiling for embedded
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i860 targets with very tight limits on stack space. Thus, we choose
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here to save the preserved registers in the upper part of the
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frame, so that we can decide at the very last minute how much (or how
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