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sse.md (define_insn "<mask_codefor>avx512dq_broadcast<mode><mask_name>_1"): Use `concat_tg_mode' attribute to determine asm register size. 

gcc/
	* config/i386/sse.md
	(define_insn "<mask_codefor>avx512dq_broadcast<mode><mask_name>_1"):
	Use `concat_tg_mode' attribute to determine asm register size.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r214571
This commit is contained in:
Alexander Ivchenko 2014-08-27 11:35:12 +00:00 committed by Kirill Yukhin
parent ca9b264e41
commit 4854de0d69
2 changed files with 21 additions and 7 deletions
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15
gcc/ChangeLog
View File

@ -7,7 +7,20 @@
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/sse.md
* config/i386/sse.md
(define_insn "<mask_codefor>avx512dq_broadcast<mode><mask_name>_1"):
Use `concat_tg_mode' attribute to determine asm register size.
2014-08-27 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/sse.md
(define_mode_iterator VI48_AVX512VL): New.
(define_mode_iterator VI_UNALIGNED_LOADSTORE): Delete.
(define_mode_iterator VI_ULOADSTORE_BW_AVX512VL): New.

13
gcc/config/i386/sse.md
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@ -718,6 +718,12 @@
(V16SF "ss") (V8SF "ss") (V4SF "ss")
(V8DF "sd") (V4DF "sd") (V2DF "sd")])
;; Tie mode of assembler operand to mode iterator
(define_mode_attr concat_tg_mode
[(V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t")
(V64QI "g") (V32HI "g") (V16SI "g") (V8DI "g") (V16SF "g") (V8DF "g")])
;; Include define_subst patterns for instructions with mask
(include "subst.md")
@ -14702,7 +14708,7 @@
(match_operand:<64x2mode> 1 "nonimmediate_operand" "v,m")))]
"TARGET_AVX512DQ"
"@
vshuf<shuffletype>64x2\t{$0x0, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x0}
vshuf<shuffletype>64x2\t{$0x0, %<concat_tg_mode>1, %<concat_tg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<concat_tg_mode>1, %<concat_tg_mode>1, 0x0}
vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
@ -15448,11 +15454,6 @@
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
;; For avx_vec_concat<mode> insn pattern
(define_mode_attr concat_tg_mode
[(V32QI "t") (V16HI "t") (V8SI "t") (V4DI "t") (V8SF "t") (V4DF "t")
(V64QI "g") (V32HI "g") (V16SI "g") (V8DI "g") (V16SF "g") (V8DF "g")])
(define_insn "avx_vec_concat<mode>"
[(set (match_operand:V_256_512 0 "register_operand" "=x,x")
(vec_concat:V_256_512