aarch64: Add support for unpacked SVE mult, max and min
This patch makes the SVE_INT_BINARY_IMM patterns support unpacked arithmetic, covering MUL, SMAX, SMIN, UMAX and UMIN. For min and max, the type suffix must be taken from the element size rather than the container size. The XFAILs are due to PR98602. gcc/ * config/aarch64/aarch64-sve.md (<SVE_INT_BINARY_IMM:optab><mode>3) (@aarch64_pred_<SVE_INT_BINARY_IMM:optab><mode>) (*post_ra_<SVE_INT_BINARY_IMM:optab><mode>3): Extend from SVE_FULL_I to SVE_I. gcc/testsuite/ PR testsuite/98602 * g++.target/aarch64/sve/max_1.C: New test. * g++.target/aarch64/sve/min_1.C: Likewise. * gcc.target/aarch64/sve/mul_2.c: Likewise.
This commit is contained in:
Richard Sandiford
parent
b81fbfe1eb
commit
48c7f5b881
@ -3628,12 +3628,12 @@
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;; Unpredicated integer binary operations that have an immediate form.
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;; Unpredicated integer binary operations that have an immediate form.
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(define_expand "<optab><mode>3"
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(define_expand "<optab><mode>3"
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[(set (match_operand:SVE_FULL_I 0 "register_operand")
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[(set (match_operand:SVE_I 0 "register_operand")
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(unspec:SVE_FULL_I
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(unspec:SVE_I
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[(match_dup 3)
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[(match_dup 3)
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(SVE_INT_BINARY_IMM:SVE_FULL_I
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(SVE_INT_BINARY_IMM:SVE_I
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(match_operand:SVE_FULL_I 1 "register_operand")
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(match_operand:SVE_I 1 "register_operand")
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(match_operand:SVE_FULL_I 2 "aarch64_sve_<sve_imm_con>_operand"))]
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(match_operand:SVE_I 2 "aarch64_sve_<sve_imm_con>_operand"))]
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UNSPEC_PRED_X))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"TARGET_SVE"
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{
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{
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@ -3647,12 +3647,12 @@
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;; and would make the instruction seem less uniform to the register
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;; and would make the instruction seem less uniform to the register
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;; allocator.
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;; allocator.
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(define_insn_and_split "@aarch64_pred_<optab><mode>"
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(define_insn_and_split "@aarch64_pred_<optab><mode>"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, w, ?&w, ?&w")
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[(set (match_operand:SVE_I 0 "register_operand" "=w, w, ?&w, ?&w")
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(unspec:SVE_FULL_I
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(unspec:SVE_I
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
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[(match_operand:<VPRED> 1 "register_operand" "Upl, Upl, Upl, Upl")
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(SVE_INT_BINARY_IMM:SVE_FULL_I
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(SVE_INT_BINARY_IMM:SVE_I
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(match_operand:SVE_FULL_I 2 "register_operand" "%0, 0, w, w")
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(match_operand:SVE_I 2 "register_operand" "%0, 0, w, w")
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(match_operand:SVE_FULL_I 3 "aarch64_sve_<sve_imm_con>_operand" "<sve_imm_con>, w, <sve_imm_con>, w"))]
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(match_operand:SVE_I 3 "aarch64_sve_<sve_imm_con>_operand" "<sve_imm_con>, w, <sve_imm_con>, w"))]
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UNSPEC_PRED_X))]
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UNSPEC_PRED_X))]
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"TARGET_SVE"
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"TARGET_SVE"
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"@
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"@
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@ -3665,7 +3665,7 @@
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"&& reload_completed
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"&& reload_completed
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&& !register_operand (operands[3], <MODE>mode)"
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&& !register_operand (operands[3], <MODE>mode)"
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[(set (match_dup 0)
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[(set (match_dup 0)
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(SVE_INT_BINARY_IMM:SVE_FULL_I (match_dup 2) (match_dup 3)))]
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(SVE_INT_BINARY_IMM:SVE_I (match_dup 2) (match_dup 3)))]
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""
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""
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[(set_attr "movprfx" "*,*,yes,yes")]
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[(set_attr "movprfx" "*,*,yes,yes")]
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)
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)
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@ -3674,10 +3674,10 @@
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;; These are generated by splitting a predicated instruction whose
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;; These are generated by splitting a predicated instruction whose
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;; predicate is unused.
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;; predicate is unused.
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(define_insn "*post_ra_<optab><mode>3"
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(define_insn "*post_ra_<optab><mode>3"
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[(set (match_operand:SVE_FULL_I 0 "register_operand" "=w, ?&w")
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[(set (match_operand:SVE_I 0 "register_operand" "=w, ?&w")
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(SVE_INT_BINARY_IMM:SVE_FULL_I
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(SVE_INT_BINARY_IMM:SVE_I
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(match_operand:SVE_FULL_I 1 "register_operand" "0, w")
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(match_operand:SVE_I 1 "register_operand" "0, w")
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(match_operand:SVE_FULL_I 2 "aarch64_sve_<sve_imm_con>_immediate")))]
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(match_operand:SVE_I 2 "aarch64_sve_<sve_imm_con>_immediate")))]
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"TARGET_SVE && reload_completed"
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"TARGET_SVE && reload_completed"
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"@
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"@
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<sve_int_op>\t%0.<Vetype>, %0.<Vetype>, #%<sve_imm_prefix>2
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<sve_int_op>\t%0.<Vetype>, %0.<Vetype>, #%<sve_imm_prefix>2
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73
gcc/testsuite/g++.target/aarch64/sve/max_1.C
Normal file
73
gcc/testsuite/g++.target/aarch64/sve/max_1.C
Normal file
@ -0,0 +1,73 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP_IMM(TYPE, OP, NAME, AMT) \
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TYPE test##_##TYPE##_##NAME (TYPE a) { return a > AMT ? a : AMT; }
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#define TEST_OP(TYPE, MINV, MAXV) \
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TYPE test##_##TYPE##_reg (TYPE a, TYPE b) { return a > b ? a : b; } \
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TEST_OP_IMM (TYPE, OP, a, MINV) \
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TEST_OP_IMM (TYPE, OP, b, 50) \
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TEST_OP_IMM (TYPE, OP, c, MAXV)
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#define TEST_TYPE(TYPE, SIZE, MINV, MAXV) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE, MINV, MAXV)
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TEST_TYPE (int8_t, 32, -100, 100)
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TEST_TYPE (uint8_t, 32, 2, 250)
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TEST_TYPE (int8_t, 64, -110, 110)
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TEST_TYPE (uint8_t, 64, 3, 253)
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TEST_TYPE (int16_t, 64, -128, 127)
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TEST_TYPE (uint16_t, 64, 4, 255)
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TEST_TYPE (int8_t, 128, -120, 120)
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TEST_TYPE (uint8_t, 128, 5, 251)
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TEST_TYPE (int16_t, 128, -128, 127)
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TEST_TYPE (uint16_t, 128, 6, 255)
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TEST_TYPE (int32_t, 128, -128, 127)
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TEST_TYPE (uint32_t, 128, 7, 255)
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-100\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #-120\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #-128\n} 2 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #-128\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #100\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #110\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.b, z[0-9]+\.b, #120\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.h, z[0-9]+\.h, #127\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tsmax\tz[0-9]+\.s, z[0-9]+\.s, #127\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #3\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #4\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #6\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #7\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #250\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #251\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.b, z[0-9]+\.b, #253\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.h, z[0-9]+\.h, #255\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tumax\tz[0-9]+\.s, z[0-9]+\.s, #255\n} 1 } } */
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73
gcc/testsuite/g++.target/aarch64/sve/min_1.C
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73
gcc/testsuite/g++.target/aarch64/sve/min_1.C
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@ -0,0 +1,73 @@
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/* { dg-do assemble { target aarch64_asm_sve_ok } } */
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/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
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#include <stdint.h>
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#define TEST_OP_IMM(TYPE, OP, NAME, AMT) \
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TYPE test##_##TYPE##_##NAME (TYPE a) { return a < AMT ? a : AMT; }
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#define TEST_OP(TYPE, MINV, MAXV) \
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TYPE test##_##TYPE##_reg (TYPE a, TYPE b) { return a < b ? a : b; } \
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TEST_OP_IMM (TYPE, OP, a, MINV) \
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TEST_OP_IMM (TYPE, OP, b, 50) \
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TEST_OP_IMM (TYPE, OP, c, MAXV)
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#define TEST_TYPE(TYPE, SIZE, MINV, MAXV) \
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typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
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TEST_OP (TYPE##SIZE, MINV, MAXV)
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TEST_TYPE (int8_t, 32, -100, 100)
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TEST_TYPE (uint8_t, 32, 2, 250)
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TEST_TYPE (int8_t, 64, -110, 110)
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TEST_TYPE (uint8_t, 64, 3, 253)
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TEST_TYPE (int16_t, 64, -128, 127)
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TEST_TYPE (uint16_t, 64, 4, 255)
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TEST_TYPE (int8_t, 128, -120, 120)
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TEST_TYPE (uint8_t, 128, 5, 251)
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TEST_TYPE (int16_t, 128, -128, 127)
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TEST_TYPE (uint16_t, 128, 6, 255)
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TEST_TYPE (int32_t, 128, -128, 127)
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TEST_TYPE (uint32_t, 128, 7, 255)
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 3 } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-100\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #-120\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #-128\n} 2 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #-128\n} 1 } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #100\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #110\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.b, z[0-9]+\.b, #120\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.h, z[0-9]+\.h, #127\n} 2 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tsmin\tz[0-9]+\.s, z[0-9]+\.s, #127\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #3\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #4\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #6\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #7\n} 1 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 3 { xfail *-*-* } } } */
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/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 2 { xfail *-*-* } } } */
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|
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 1 { xfail *-*-* } } } */
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #250\n} 1 { xfail *-*-* } } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #251\n} 1 { xfail *-*-* } } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.b, z[0-9]+\.b, #253\n} 1 { xfail *-*-* } } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.h, z[0-9]+\.h, #255\n} 2 { xfail *-*-* } } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tumin\tz[0-9]+\.s, z[0-9]+\.s, #255\n} 1 { xfail *-*-* } } } */
|
||||||
52
gcc/testsuite/gcc.target/aarch64/sve/mul_2.c
Normal file
52
gcc/testsuite/gcc.target/aarch64/sve/mul_2.c
Normal file
@ -0,0 +1,52 @@
|
|||||||
|
/* { dg-do assemble { target aarch64_asm_sve_ok } } */
|
||||||
|
/* { dg-options "-O -msve-vector-bits=2048 -save-temps" } */
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
#define TEST_OP_IMM(TYPE, OP, NAME, AMT) \
|
||||||
|
TYPE test##_##TYPE##_##NAME (TYPE a) { return a * AMT; }
|
||||||
|
|
||||||
|
#define TEST_OP(TYPE, MINV, MAXV) \
|
||||||
|
TYPE test##_##TYPE##_reg (TYPE a, TYPE b) { return a * b; } \
|
||||||
|
TEST_OP_IMM (TYPE, OP, a, MINV) \
|
||||||
|
TEST_OP_IMM (TYPE, OP, b, 50) \
|
||||||
|
TEST_OP_IMM (TYPE, OP, c, MAXV)
|
||||||
|
|
||||||
|
#define TEST_TYPE(TYPE, SIZE, MINV, MAXV) \
|
||||||
|
typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \
|
||||||
|
TEST_OP (TYPE##SIZE, MINV, MAXV)
|
||||||
|
|
||||||
|
TEST_TYPE (int8_t, 32, -100, 100)
|
||||||
|
TEST_TYPE (uint8_t, 32, 2, 250)
|
||||||
|
|
||||||
|
TEST_TYPE (int8_t, 64, -110, 110)
|
||||||
|
TEST_TYPE (uint8_t, 64, 3, 253)
|
||||||
|
TEST_TYPE (int16_t, 64, -128, 123)
|
||||||
|
TEST_TYPE (uint16_t, 64, 3, 255)
|
||||||
|
|
||||||
|
TEST_TYPE (int8_t, 128, -120, 120)
|
||||||
|
TEST_TYPE (uint8_t, 128, 4, 251)
|
||||||
|
TEST_TYPE (int16_t, 128, -128, 123)
|
||||||
|
TEST_TYPE (uint16_t, 128, 2, 255)
|
||||||
|
TEST_TYPE (int32_t, 128, -128, 123)
|
||||||
|
TEST_TYPE (uint32_t, 128, 4, 255)
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b, z[0-9]+\.b\n} 6 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-100\n} 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-110\n} 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #-120\n} 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #-128\n} 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #-128\n} 1 } } */
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #50\n} 6 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #50\n} 4 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #50\n} 2 } } */
|
||||||
|
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #100\n} 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #110\n} 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.b, z[0-9]+\.b, #120\n} 1 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.h, z[0-9]+\.h, #123\n} 2 } } */
|
||||||
|
/* { dg-final { scan-assembler-times {\tmul\tz[0-9]+\.s, z[0-9]+\.s, #123\n} 1 } } */
|
||||||
Loading…
Reference in New Issue
Block a user