sparc.h (FIXED_REGISTERS): Add %icc.
* config/sparc/sparc.h (FIXED_REGISTERS): Add %icc. * config/visium/visium.c (visium_expand_int_cstore): Revert latest change. (visium_expand_fp_cstore): Likewise. From-SVN: r240892
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@ -1,3 +1,11 @@
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2016-10-08 Eric Botcazou <ebotcazou@adacore.com>
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* config/sparc/sparc.h (FIXED_REGISTERS): Add %icc.
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* config/visium/visium.c (visium_expand_int_cstore): Revert latest
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change.
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(visium_expand_fp_cstore): Likewise.
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2016-10-08 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
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* diagnostic-core.h (warning_at_rich_loc_n): Declare.
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@ -603,7 +603,8 @@ extern enum cmodel sparc_cmodel;
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(e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
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32+32+32+4 == 100.
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Register 100 is used as the integer condition code register.
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Register 101 is used as the soft frame pointer register. */
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Register 101 is used as the soft frame pointer register.
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Register 102 is used as the general status register by VIS instructions. */
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#define FIRST_PSEUDO_REGISTER 103
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@ -678,7 +679,7 @@ extern enum cmodel sparc_cmodel;
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, \
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\
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0, 0, 0, 0, 0, 1, 1}
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0, 0, 0, 0, 1, 1, 1}
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/* 1 for registers not available across function calls.
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These must include the FIXED_REGISTERS and also any
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@ -885,12 +886,7 @@ extern int sparc_mode_class[];
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have a class that is the union of FPCC_REGS with either of the others,
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it is important that it appear first. Otherwise the compiler will die
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trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
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constraints.
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It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
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may try to use it to hold an SImode value. See register_operand.
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??? Should %fcc[0123] be handled similarly?
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*/
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constraints. */
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enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
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EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
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@ -2222,7 +2222,7 @@ visium_expand_int_cstore (rtx *operands, enum machine_mode mode)
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code = reverse_condition (code);
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reverse = true;
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/* fall through */
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/* ... fall through ... */
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case LTU:
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case GTU:
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@ -2270,7 +2270,7 @@ visium_expand_fp_cstore (rtx *operands,
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code = reverse_condition_maybe_unordered (code);
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reverse = true;
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/* fall through */
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/* ... fall through ... */
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case LT:
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case GT:
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