Fix bitfield insert/extract aliasing problem found by GNAT.
* mips.md (insv, extzv, extv): Add change_address call. (movsi_ulw, movsi_usw): Change QImode to BLKmode in pattern. From-SVN: r16331
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@ -1,5 +1,8 @@
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Tue Nov 4 16:55:11 1997 Jim Wilson <wilson@cygnus.com>
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* mips.md (insv, extzv, extv): Add change_address call.
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(movsi_ulw, movsi_usw): Change QImode to BLKmode in pattern.
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* integrate.c (save_for_inline_copying): Copy parm_reg_stack_loc.
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* reload.c (find_reloads, case 'm' and 'o'): Reject HIGH constants.
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@ -3152,6 +3152,9 @@ move\\t%0,%z4\\n\\
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if (GET_CODE (operands[1]) != MEM)
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FAIL;
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/* Change the mode to BLKmode for aliasing purposes. */
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operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
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/* Otherwise, emit a lwl/lwr pair to load the value. */
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emit_insn (gen_movsi_ulw (operands[0], operands[1]));
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DONE;
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@ -3176,6 +3179,9 @@ move\\t%0,%z4\\n\\
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if (GET_CODE (operands[1]) != MEM)
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FAIL;
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/* Change the mode to BLKmode for aliasing purposes. */
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operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
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/* Otherwise, emit a lwl/lwr pair to load the value. */
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emit_insn (gen_movsi_ulw (operands[0], operands[1]));
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DONE;
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@ -3200,6 +3206,9 @@ move\\t%0,%z4\\n\\
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if (GET_CODE (operands[0]) != MEM)
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FAIL;
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/* Change the mode to BLKmode for aliasing purposes. */
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operands[0] = change_address (operands[0], BLKmode, XEXP (operands[0], 0));
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/* Otherwise, emit a swl/swr pair to load the value. */
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emit_insn (gen_movsi_usw (operands[0], operands[3]));
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DONE;
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@ -3209,7 +3218,7 @@ move\\t%0,%z4\\n\\
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(define_insn "movsi_ulw"
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[(set (match_operand:SI 0 "register_operand" "=&d,&d")
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(unspec:SI [(match_operand:QI 1 "general_operand" "R,o")] 0))]
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(unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
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""
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"*
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{
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@ -3237,8 +3246,8 @@ move\\t%0,%z4\\n\\
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(set_attr "length" "2,4")])
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(define_insn "movsi_usw"
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[(set (match_operand:QI 0 "memory_operand" "=R,o")
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(unspec:QI [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
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[(set (match_operand:BLK 0 "memory_operand" "=R,o")
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(unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
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""
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"*
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{
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