Mark Power10 fusion option undocumented and remove sub-options.

gcc/
	* config/rs6000/rs6000.opt (mpower10-fusion): Mark Undocumented.
	(mpower10-fusion-ld-cmpi, mpower10-fusion-2logical,
	mpower10-fusion-logical-add, mpower10-fusion-add-logical,
	mpower10-fusion-2add, mpower10-fusion-2store): Remove.
	* config/rs6000/rs6000-cpus.def (ISA_3_1_MASKS_SERVER,
	OTHER_P9_VECTOR_MASKS): Remove Power10 fusion sub-options.
	* config/rs6000/rs6000.cc (rs6000_option_override_internal,
	power10_sched_reorder): Likewise.
	* config/rs6000/genfusion.pl (gen_ld_cmpi_p10, gen_logical_addsubf,
	gen_addadd): Likewise
	* config/rs6000/fusion.md: Regenerate.
This commit is contained in:
Pat Haugen 2022-02-18 15:38:23 -06:00
parent 20a33efdf3
commit 4984f882f4
5 changed files with 174 additions and 238 deletions

File diff suppressed because it is too large Load Diff

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@ -118,7 +118,7 @@ sub gen_ld_cmpi_p10
} else {
print " (set (match_operand:${result} 0 \"gpc_reg_operand\" \"=r\") (${extend}_extend:${result} (match_dup 1)))]\n";
}
print " \"(TARGET_P10_FUSION && TARGET_P10_FUSION_LD_CMPI)\"\n";
print " \"(TARGET_P10_FUSION)\"\n";
print " \"l${ldst}${echr}%X1 %0,%1\\;cmp${cmpl}di %2,%0,%3\"\n";
print " \"&& reload_completed\n";
print " && (cc_reg_not_cr0_operand (operands[2], CCmode)\n";
@ -166,8 +166,8 @@ sub gen_logical_addsubf
$outer_op, $outer_comp, $outer_inv, $outer_rtl, $inner, @inner_ops,
$inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4,
$bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp,
$target_flag, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,
$outer_name, $fuse_type);
$ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name,
$fuse_type);
KIND: foreach $kind ('scalar','vector') {
@outer_ops = @logicals;
if ( $kind eq 'vector' ) {
@ -199,18 +199,15 @@ sub gen_logical_addsubf
$outer_rtl = $rtlop{$outer};
@inner_ops = @logicals;
$ftype = "logical-logical";
$target_flag = "TARGET_P10_FUSION_2LOGICAL";
if ( exists $isaddsub{$outer} ) {
@inner_ops = sort keys %logicals_addsub;
$ftype = "logical-add";
$target_flag = "TARGET_P10_FUSION_LOGADD";
} elsif ( $kind ne 'vector' && exists $logicals_addsub{$outer} ) {
push (@inner_ops, @addsub);
}
INNER: foreach $inner ( @inner_ops ) {
if ( exists $isaddsub{$inner} ) {
$ftype = "add-logical";
$target_flag = "TARGET_P10_FUSION_ADDLOG";
}
$inner_comp = $complement{$inner};
$inner_inv = $invert{$inner};
@ -266,7 +263,7 @@ sub gen_logical_addsubf
[(set (match_operand:${mode} 3 "${pred}" "=&0,&1,&${constraint},${constraint}")
${outer_exp})
(clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint}"))]
"(TARGET_P10_FUSION && $target_flag)"
"(TARGET_P10_FUSION)"
"@
${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32}
@ -313,7 +310,7 @@ sub gen_addadd
(match_operand:${mode} 1 "${pred}" "%${c4}"))
(match_operand:${mode} 2 "${pred}" "${c4}")))
(clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint}"))]
"(TARGET_P10_FUSION && TARGET_P10_FUSION_2ADD)"
"(TARGET_P10_FUSION)"
"@
${op} %3,%1,%0\\;${op} %3,%3,%2
${op} %3,%1,%0\\;${op} %3,%3,%2

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@ -85,13 +85,7 @@
#define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \
| OPTION_MASK_POWER10 \
| OTHER_POWER10_MASKS \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
| OPTION_MASK_P10_FUSION_2STORE)
| OPTION_MASK_P10_FUSION)
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
@ -139,12 +133,6 @@
| OPTION_MASK_FPRND \
| OPTION_MASK_POWER10 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_P10_FUSION_LD_CMPI \
| OPTION_MASK_P10_FUSION_2LOGICAL \
| OPTION_MASK_P10_FUSION_LOGADD \
| OPTION_MASK_P10_FUSION_ADDLOG \
| OPTION_MASK_P10_FUSION_2ADD \
| OPTION_MASK_P10_FUSION_2STORE \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \

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@ -4446,30 +4446,6 @@ rs6000_option_override_internal (bool global_init_p)
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
if (TARGET_POWER10 &&
(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LD_CMPI) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LD_CMPI;
if (TARGET_POWER10
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2LOGICAL) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2LOGICAL;
if (TARGET_POWER10
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_LOGADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_LOGADD;
if (TARGET_POWER10
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ADDLOG) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ADDLOG;
if (TARGET_POWER10
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2ADD) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2ADD;
if (TARGET_POWER10
&& (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2STORE) == 0)
rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2STORE;
/* Turn off vector pair/mma options on non-power10 systems. */
else if (!TARGET_POWER10 && TARGET_MMA)
{
@ -19032,8 +19008,7 @@ power10_sched_reorder (rtx_insn **ready, int lastpos)
/* Try to pair certain store insns to adjacent memory locations
so that the hardware will fuse them to a single operation. */
if (TARGET_P10_FUSION && TARGET_P10_FUSION_2STORE
&& is_fusable_store (last_scheduled_insn, &mem1))
if (TARGET_P10_FUSION && is_fusable_store (last_scheduled_insn, &mem1))
{
/* A fusable store was just scheduled. Scan the ready list for another

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@ -487,33 +487,9 @@ Target Mask(P8_VECTOR) Var(rs6000_isa_flags)
Use vector and scalar instructions added in ISA 2.07.
mpower10-fusion
Target Mask(P10_FUSION) Var(rs6000_isa_flags)
Target Undocumented Mask(P10_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power10.
mpower10-fusion-ld-cmpi
Target Undocumented Mask(P10_FUSION_LD_CMPI) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power10.
mpower10-fusion-2logical
Target Undocumented Mask(P10_FUSION_2LOGICAL) Var(rs6000_isa_flags)
Fuse pairs of scalar or vector logical operations together for better performance on power10.
mpower10-fusion-logical-add
Target Undocumented Mask(P10_FUSION_LOGADD) Var(rs6000_isa_flags)
Fuse scalar logical op with add/subf for better performance on power10.
mpower10-fusion-add-logical
Target Undocumented Mask(P10_FUSION_ADDLOG) Var(rs6000_isa_flags)
Fuse scalar add/subf with logical op for better performance on power10.
mpower10-fusion-2add
Target Undocumented Mask(P10_FUSION_2ADD) Var(rs6000_isa_flags)
Fuse dependent pairs of add or vaddudm instructions for better performance on power10.
mpower10-fusion-2store
Target Undocumented Mask(P10_FUSION_2STORE) Var(rs6000_isa_flags)
Fuse certain store operations together for better performance on power10.
mcrypto
Target Mask(CRYPTO) Var(rs6000_isa_flags)
Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.