i386.md (*zero_extendsidi2): Enable alternative (?r, *Yj) also for 32bit target.
* config/i386/i386.md (*zero_extendsidi2): Enable alternative (?r, *Yj) also for 32bit target. Update insn attributes. (zero-extendsidi2 splitter): Allow all registers for operand 1. From-SVN: r248757
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@ -1,3 +1,9 @@
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2017-05-31 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (*zero_extendsidi2): Enable alternative (?r, *Yj)
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also for 32bit target. Update insn attributes.
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(zero-extendsidi2 splitter): Allow all registers for operand 1.
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2017-05-31 Sebastian Peryt <sebastian.peryt@intel.com>
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* config/i386/avx512fintrin.h (_mm_mask_max_sd)
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@ -3843,7 +3843,7 @@
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "0,1,2")
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(const_string "nox64")
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(eq_attr "alternative" "3,7")
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(eq_attr "alternative" "3")
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(const_string "x64")
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(eq_attr "alternative" "9")
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(const_string "sse2")
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@ -3860,7 +3860,11 @@
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(const_string "multi")
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(eq_attr "alternative" "5,6")
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(const_string "mmxmov")
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(eq_attr "alternative" "7,8,9,10,11")
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(eq_attr "alternative" "7")
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(if_then_else (match_test "TARGET_64BIT")
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(const_string "ssemov")
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(const_string "multi"))
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(eq_attr "alternative" "8,9,10,11")
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(const_string "ssemov")
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(eq_attr "alternative" "12")
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(const_string "mskmov")
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@ -3881,7 +3885,10 @@
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(set (attr "mode")
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(cond [(eq_attr "alternative" "5,6")
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(const_string "DI")
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(eq_attr "alternative" "7,8,10,11")
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(and (eq_attr "alternative" "7")
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(match_test "TARGET_64BIT"))
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(const_string "TI")
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(eq_attr "alternative" "8,10,11")
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(const_string "TI")
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]
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(const_string "SI")))])
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@ -3903,7 +3910,7 @@
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(define_split
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[(set (match_operand:DI 0 "nonimmediate_gr_operand")
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_gr_operand")))]
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(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]
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"!TARGET_64BIT && reload_completed
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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[(set (match_dup 3) (match_dup 1))
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