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re PR target/20924 (inline float divide does not set correct fpu status flags)

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PR target/20924
	* config/ia64/ia64.md (divsf3_internal_lat): Generate frcpa with
	fpsr 0 instead of fpsr 1.
	(divsf3_internal_thr): Ditto.
	(divdf3_internal_lat): Ditto.
	(divdf3_internal_thr): Ditto.
	(divxf3_internal_lat): Ditto.
	(divxf3_internal_thr): Ditto.

From-SVN: r98095
This commit is contained in:
Steve Ellcey 2005-04-13 15:57:37 +00:00 committed by Steve Ellcey
parent 41f717fb6b
commit 4a36a3f164
2 changed files with 17 additions and 6 deletions
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11
gcc/ChangeLog
View File

@ -1,3 +1,14 @@
2005-04-13 Steve Ellcey <sje@cup.hp.com>
PR target/20924
* config/ia64/ia64.md (divsf3_internal_lat): Generate frcpa with
fpsr 0 instead of fpsr 1.
(divsf3_internal_thr): Ditto.
(divdf3_internal_lat): Ditto.
(divdf3_internal_thr): Ditto.
(divxf3_internal_lat): Ditto.
(divxf3_internal_thr): Ditto.
2005-04-13 Kazu Hirata <kazu@cs.umass.edu>
PR tree-optimization/20913

12
gcc/config/ia64/ia64.md
View File

@ -2699,7 +2699,7 @@
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6)))
(use (const_int 1))]))
@ -2756,7 +2756,7 @@
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
@ -3182,7 +3182,7 @@
[(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
(set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(use (const_int 0))])
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7)))
(use (const_int 1))]))
@ -3262,7 +3262,7 @@
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
@ -3847,7 +3847,7 @@
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(use (const_int 0))])
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 8)
@ -3925,7 +3925,7 @@
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
(use (const_int 1))])
(use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 6)