From 4a5528ccf5d3d6a3c93bb40b404257ba41d51b2a Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Wed, 14 Apr 2010 18:16:31 +0200 Subject: [PATCH] i386.md (maxmin_int): Rename code attribute from maxminiprefix and update all users. * config/i386/i386.md (maxmin_int): Rename code attribute from maxminiprefix and update all users. (maxmin_float): Ditto from maxminfprefix. (logic): Ditto from logicprefix. (absneg_mnemonic): Ditto from absnegprefix. * config/i386/mmx.md: Update all users of maxminiprefix, maxminfprefix and loficprefix for rename. * config/i386/sse.md: Ditto. * config/i386/sync.md (sync_): Update for logicprefix rename. From-SVN: r158350 --- gcc/ChangeLog | 13 ++++++++++ gcc/config/i386/i386.md | 56 ++++++++++++++++++++--------------------- gcc/config/i386/mmx.md | 10 ++++---- gcc/config/i386/sse.md | 40 ++++++++++++++--------------- gcc/config/i386/sync.md | 2 +- 5 files changed, 67 insertions(+), 54 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 98193265a61..f702110c332 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2010-04-14 Uros Bizjak + + * config/i386/i386.md (maxmin_int): Rename code attribute from + maxminiprefix and update all users. + (maxmin_float): Ditto from maxminfprefix. + (logic): Ditto from logicprefix. + (absneg_mnemonic): Ditto from absnegprefix. + * config/i386/mmx.md: Update all users of maxminiprefix, + maxminfprefix and loficprefix for rename. + * config/i386/sse.md: Ditto. + * config/i386/sync.md (sync_): Update for + logicprefix rename. + 2010-04-14 Manuel López-Ibáñez PR 42966 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a0e5d1a3a52..557bb3b1465 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -713,16 +713,16 @@ (define_code_iterator maxmin [smax smin umax umin]) ;; Base name for integer and FP insn mnemonic -(define_code_attr maxminiprefix [(smax "maxs") (smin "mins") - (umax "maxu") (umin "minu")]) -(define_code_attr maxminfprefix [(smax "max") (smin "min")]) +(define_code_attr maxmin_int [(smax "maxs") (smin "mins") + (umax "maxu") (umin "minu")]) +(define_code_attr maxmin_float [(smax "max") (smin "min")]) ;; Mapping of logic operators (define_code_iterator any_logic [and ior xor]) (define_code_iterator any_or [ior xor]) ;; Base name for insn mnemonic. -(define_code_attr logicprefix [(and "and") (ior "or") (xor "xor")]) +(define_code_attr logic [(and "and") (ior "or") (xor "xor")]) ;; Mapping of shift-right operators (define_code_iterator any_shiftrt [lshiftrt ashiftrt]) @@ -746,7 +746,7 @@ (define_code_iterator absneg [abs neg]) ;; Base name for x87 insn mnemonic. -(define_code_attr absnegprefix [(abs "abs") (neg "chs")]) +(define_code_attr absneg_mnemonic [(abs "abs") (neg "chs")]) ;; Used in signed and unsigned widening multiplications. (define_code_iterator any_extend [sign_extend zero_extend]) @@ -8785,7 +8785,7 @@ (match_operand:SWI248 2 "" ",r"))) (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, mode, operands)" - "{}\t{%2, %0|%0, %2}" + "{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) @@ -8797,9 +8797,9 @@ (clobber (reg:CC FLAGS_REG))] "ix86_binary_operator_ok (, QImode, operands)" "@ - {b}\t{%2, %0|%0, %2} - {b}\t{%2, %0|%0, %2} - {l}\t{%k2, %k0|%k0, %k2}" + {b}\t{%2, %0|%0, %2} + {b}\t{%2, %0|%0, %2} + {l}\t{%k2, %k0|%k0, %k2}" [(set_attr "type" "alu") (set_attr "mode" "QI,QI,SI")]) @@ -8811,7 +8811,7 @@ (match_operand:SI 2 "general_operand" "g")))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (, SImode, operands)" - "{l}\t{%2, %k0|%k0, %2}" + "{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) @@ -8822,7 +8822,7 @@ (match_operand:DI 2 "x86_64_zext_immediate_operand" "Z"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && ix86_binary_operator_ok (, SImode, operands)" - "{l}\t{%2, %k0|%k0, %2}" + "{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) @@ -8833,7 +8833,7 @@ (clobber (reg:CC FLAGS_REG))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "{b}\t{%1, %0|%0, %1}" + "{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -8847,7 +8847,7 @@ (any_or:SWI (match_dup 1) (match_dup 2)))] "ix86_match_ccmode (insn, CCNOmode) && ix86_binary_operator_ok (, mode, operands)" - "{}\t{%2, %0|%0, %2}" + "{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) @@ -8862,7 +8862,7 @@ (zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) && ix86_binary_operator_ok (, SImode, operands)" - "{l}\t{%2, %k0|%k0, %2}" + "{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) @@ -8876,7 +8876,7 @@ (any_or:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode) && ix86_binary_operator_ok (, SImode, operands)" - "{l}\t{%2, %k0|%k0, %2}" + "{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) @@ -8890,7 +8890,7 @@ "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && ix86_match_ccmode (insn, CCNOmode) && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "{b}\t{%1, %0|%0, %1}" + "{b}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "mode" "QI")]) @@ -8903,7 +8903,7 @@ (clobber (match_scratch:SWI 0 "="))] "ix86_match_ccmode (insn, CCNOmode) && ix86_binary_operator_ok (, mode, operands)" - "{}\t{%2, %0|%0, %2}" + "{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) @@ -8919,7 +8919,7 @@ (match_operand 2 "const_int_operand" "n"))) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" - "{b}\t{%2, %h0|%h0, %2}" + "{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") (set_attr "length_immediate" "1") (set_attr "modrm" "1") @@ -8939,7 +8939,7 @@ (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))" - "{b}\t{%2, %h0|%h0, %2}" + "{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) @@ -8958,7 +8958,7 @@ (clobber (reg:CC FLAGS_REG))] "!TARGET_64BIT && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))" - "{b}\t{%2, %h0|%h0, %2}" + "{b}\t{%2, %h0|%h0, %2}" [(set_attr "type" "alu") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) @@ -8976,7 +8976,7 @@ (const_int 8)))) (clobber (reg:CC FLAGS_REG))] "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)" - "{b}\t{%h2, %h0|%h0, %h2}" + "{b}\t{%h2, %h0|%h0, %h2}" [(set_attr "type" "alu") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) @@ -9366,7 +9366,7 @@ "TARGET_80387 && (reload_completed || !(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH))" - "f" + "f" [(set_attr "type" "fsgn") (set_attr "mode" "")]) @@ -9375,7 +9375,7 @@ (absneg:DF (float_extend:DF (match_operand:SF 1 "register_operand" "0"))))] "TARGET_80387 && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)" - "f" + "f" [(set_attr "type" "fsgn") (set_attr "mode" "DF")]) @@ -9384,16 +9384,16 @@ (absneg:XF (float_extend:XF (match_operand:SF 1 "register_operand" "0"))))] "TARGET_80387" - "f" + "f" [(set_attr "type" "fsgn") (set_attr "mode" "XF")]) (define_insn "*extenddfxf2" [(set (match_operand:XF 0 "register_operand" "=f") (absneg:XF (float_extend:XF - (match_operand:DF 1 "register_operand" "0"))))] + (match_operand:DF 1 "register_operand" "0"))))] "TARGET_80387" - "f" + "f" [(set_attr "type" "fsgn") (set_attr "mode" "XF")]) @@ -16898,7 +16898,7 @@ (match_operand:MODEF 1 "nonimmediate_operand" "%x") (match_operand:MODEF 2 "nonimmediate_operand" "xm")))] "AVX_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" - "vs\t{%2, %1, %0|%0, %1, %2}" + "vs\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -16909,7 +16909,7 @@ (match_operand:MODEF 1 "nonimmediate_operand" "%0") (match_operand:MODEF 2 "nonimmediate_operand" "xm")))] "SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH" - "s\t{%2, %0|%0, %2}" + "s\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 5551bcb48f3..af19732624a 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -396,7 +396,7 @@ (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW && flag_finite_math_only && ix86_binary_operator_ok (, V2SFmode, operands)" - "pf\t{%2, %0|%0, %2}" + "pf\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "prefix_extra" "1") (set_attr "mode" "V2SF")]) @@ -407,7 +407,7 @@ (match_operand:V2SF 1 "register_operand" "0") (match_operand:V2SF 2 "nonimmediate_operand" "ym")))] "TARGET_3DNOW" - "pf\t{%2, %0|%0, %2}" + "pf\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "prefix_extra" "1") (set_attr "mode" "V2SF")]) @@ -970,7 +970,7 @@ (match_operand:V4HI 2 "nonimmediate_operand" "ym")))] "(TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (, V4HImode, operands)" - "pw\t{%2, %0|%0, %2}" + "pw\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) @@ -989,7 +989,7 @@ (match_operand:V8QI 2 "nonimmediate_operand" "ym")))] "(TARGET_SSE || TARGET_3DNOW_A) && ix86_binary_operator_ok (, V8QImode, operands)" - "pb\t{%2, %0|%0, %2}" + "pb\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) @@ -1099,7 +1099,7 @@ (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] "TARGET_MMX && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f98913697b1..0baefd84705 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1015,7 +1015,7 @@ (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] "AVX_VEC_FLOAT_MODE_P (mode) && flag_finite_math_only && ix86_binary_operator_ok (, mode, operands)" - "vp\t{%2, %1, %0|%0, %1, %2}" + "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -1027,7 +1027,7 @@ (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode) && flag_finite_math_only && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) @@ -1037,7 +1037,7 @@ (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x") (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] "AVX_VEC_FLOAT_MODE_P (mode)" - "vp\t{%2, %1, %0|%0, %1, %2}" + "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseadd") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -1048,7 +1048,7 @@ (match_operand:SSEMODEF2P 1 "register_operand" "0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) @@ -1061,7 +1061,7 @@ (match_dup 1) (const_int 1)))] "AVX128_VEC_FLOAT_MODE_P (mode)" - "vs\t{%2, %1, %0|%0, %1, %2}" + "vs\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sse") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -1075,7 +1075,7 @@ (match_dup 1) (const_int 1)))] "SSE_VEC_FLOAT_MODE_P (mode)" - "s\t{%2, %0|%0, %2}" + "s\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) @@ -1597,7 +1597,7 @@ (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))] "AVX_VEC_FLOAT_MODE_P (mode) && ix86_binary_operator_ok (, mode, operands)" - "vp\t{%2, %1, %0|%0, %1, %2}" + "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -1617,7 +1617,7 @@ (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode) && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "")]) @@ -1673,7 +1673,7 @@ (match_operand:MODEF 1 "register_operand" "x") (match_operand:MODEF 2 "register_operand" "x")))] "AVX_FLOAT_MODE_P (mode)" - "vp\t{%2, %1, %0|%0, %1, %2}" + "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -1684,7 +1684,7 @@ (match_operand:MODEF 1 "register_operand" "0") (match_operand:MODEF 2 "register_operand" "x")))] "SSE_FLOAT_MODE_P (mode)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "")]) @@ -6031,7 +6031,7 @@ (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x") (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))] "TARGET_AVX && ix86_binary_operator_ok (, mode, operands)" - "vp\t{%2, %1, %0|%0, %1, %2}" + "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseiadd") (set (attr "prefix_extra") (if_then_else @@ -6056,7 +6056,7 @@ (match_operand:V16QI 1 "nonimmediate_operand" "%0") (match_operand:V16QI 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (, V16QImode, operands)" - "pb\t{%2, %0|%0, %2}" + "pb\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -6075,7 +6075,7 @@ (match_operand:V8HI 1 "nonimmediate_operand" "%0") (match_operand:V8HI 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (, V8HImode, operands)" - "pw\t{%2, %0|%0, %2}" + "pw\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -6130,7 +6130,7 @@ (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) @@ -6186,7 +6186,7 @@ (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0") (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))] "TARGET_SSE4_1 && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_extra" "1") (set_attr "mode" "TI")]) @@ -6518,7 +6518,7 @@ (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))] "TARGET_AVX && ix86_binary_operator_ok (, mode, operands)" - "vps\t{%2, %1, %0|%0, %1, %2}" + "vps\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "")]) @@ -6530,7 +6530,7 @@ (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] "(TARGET_SSE && !TARGET_SSE2) && ix86_binary_operator_ok (, mode, operands)" - "ps\t{%2, %0|%0, %2}" + "ps\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "V4SF")]) @@ -6541,7 +6541,7 @@ (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] "TARGET_AVX && ix86_binary_operator_ok (, mode, operands)" - "vp\t{%2, %1, %0|%0, %1, %2}" + "vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sselog") (set_attr "prefix" "vex") (set_attr "mode" "TI")]) @@ -6552,7 +6552,7 @@ (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) @@ -6571,7 +6571,7 @@ (match_operand:TF 1 "nonimmediate_operand" "%0") (match_operand:TF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && ix86_binary_operator_ok (, TFmode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index feea16176bf..0fb10bc972e 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -236,4 +236,4 @@ UNSPECV_LOCK)) (clobber (reg:CC FLAGS_REG))] "" - "lock{%;| }{}\t{%1, %0|%0, %1}") + "lock{%;| }{}\t{%1, %0|%0, %1}")