S/390: arch13: Support new bit operations
Make use of the new bit operation instructions when generating code
for the arch13 level.
gcc/ChangeLog:
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
* config/s390/s390.c (s390_canonicalize_comparison): Convert
certain compares for arch13 in order to make use of the condition
code result produced by the new instructions.
(s390_rtx_costs): Adjust the costs for nnrk, nngrk, nork, nogrk,
nxrk, and nxgrk instruction patterns.
* config/s390/s390.md (ANDOR, bitops_name, inv_bitops_name)
(inv_no): Add new code iterator together with some attributes.
("*andc_split_<mode>"): Disable splitter for arch13.
("*<ANDOR:bitops_name>c<GPR:mode>_cc")
("*<ANDOR:bitops_name>c<GPR:mode>_cconly")
("*<ANDOR:bitops_name>c<GPR:mode>")
("*n<ANDOR:inv_bitops_name><GPR:mode>_cc")
("*n<ANDOR:inv_bitops_name><mode>_cconly")
("*n<ANDOR:inv_bitops_name><mode>", "*nxor<GPR:mode>_cc")
("*nxor<mode>_cconly", "*nxor<mode>"): New insn definitions.
gcc/testsuite/ChangeLog:
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
* gcc.target/s390/arch13/bitops-1.c: New test.
* gcc.target/s390/arch13/bitops-2.c: New test.
* gcc.target/s390/md/andc-splitter-1.c: Add -march=z14 build
option and adjust line numbers.
* gcc.target/s390/md/andc-splitter-2.c: Likewise.
From-SVN: r270078
This commit is contained in:
Andreas Krebbel
Andreas Krebbel
parent
511ea1538b
commit
4a9733f3df
@ -1,3 +1,21 @@
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2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
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* config/s390/s390.c (s390_canonicalize_comparison): Convert
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certain compares for arch13 in order to make use of the condition
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code result produced by the new instructions.
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(s390_rtx_costs): Adjust the costs for nnrk, nngrk, nork, nogrk,
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nxrk, and nxgrk instruction patterns.
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* config/s390/s390.md (ANDOR, bitops_name, inv_bitops_name)
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(inv_no): Add new code iterator together with some attributes.
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("*andc_split_<mode>"): Disable splitter for arch13.
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("*<ANDOR:bitops_name>c<GPR:mode>_cc")
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("*<ANDOR:bitops_name>c<GPR:mode>_cconly")
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("*<ANDOR:bitops_name>c<GPR:mode>")
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("*n<ANDOR:inv_bitops_name><GPR:mode>_cc")
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("*n<ANDOR:inv_bitops_name><mode>_cconly")
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("*n<ANDOR:inv_bitops_name><mode>", "*nxor<GPR:mode>_cc")
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("*nxor<mode>_cconly", "*nxor<mode>"): New insn definitions.
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2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
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* common/config/s390/s390-common.c (processor_flags_table): New
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@ -1793,6 +1793,38 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
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*op0 = XEXP (*op0, 0);
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}
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}
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/* ~a==b -> ~(a^b)==0 ~a!=b -> ~(a^b)!=0 */
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if (TARGET_ARCH13
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&& (*code == EQ || *code == NE)
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&& (GET_MODE (*op0) == DImode || GET_MODE (*op0) == SImode)
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&& GET_CODE (*op0) == NOT)
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{
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machine_mode mode = GET_MODE (*op0);
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*op0 = gen_rtx_XOR (mode, XEXP (*op0, 0), *op1);
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*op0 = gen_rtx_NOT (mode, *op0);
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*op1 = const0_rtx;
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}
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/* a&b == -1 -> ~a|~b == 0 a|b == -1 -> ~a&~b == 0 */
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if (TARGET_ARCH13
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&& (*code == EQ || *code == NE)
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&& (GET_CODE (*op0) == AND || GET_CODE (*op0) == IOR)
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&& (GET_MODE (*op0) == DImode || GET_MODE (*op0) == SImode)
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&& CONST_INT_P (*op1)
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&& *op1 == constm1_rtx)
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{
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machine_mode mode = GET_MODE (*op0);
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rtx op00 = gen_rtx_NOT (mode, XEXP (*op0, 0));
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rtx op01 = gen_rtx_NOT (mode, XEXP (*op0, 1));
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if (GET_CODE (*op0) == AND)
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*op0 = gen_rtx_IOR (mode, op00, op01);
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else
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*op0 = gen_rtx_AND (mode, op00, op01);
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*op1 = const0_rtx;
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}
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}
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@ -3516,6 +3548,21 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
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return true;
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}
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case IOR:
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/* nnrk, nngrk */
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if (TARGET_ARCH13
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&& (mode == SImode || mode == DImode)
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&& GET_CODE (XEXP (x, 0)) == NOT
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&& GET_CODE (XEXP (x, 1)) == NOT)
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{
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*total = COSTS_N_INSNS (1);
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if (!REG_P (XEXP (XEXP (x, 0), 0)))
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*total += 1;
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if (!REG_P (XEXP (XEXP (x, 1), 0)))
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*total += 1;
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return true;
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}
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/* risbg */
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if (GET_CODE (XEXP (x, 0)) == AND
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&& GET_CODE (XEXP (x, 1)) == ASHIFT
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@ -3544,19 +3591,33 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
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*total = COSTS_N_INSNS (1);
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return true;
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}
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*total = COSTS_N_INSNS (1);
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return false;
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case AND:
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/* nork, nogrk */
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if (TARGET_ARCH13
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&& (mode == SImode || mode == DImode)
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&& GET_CODE (XEXP (x, 0)) == NOT
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&& GET_CODE (XEXP (x, 1)) == NOT)
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{
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*total = COSTS_N_INSNS (1);
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if (!REG_P (XEXP (XEXP (x, 0), 0)))
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*total += 1;
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if (!REG_P (XEXP (XEXP (x, 1), 0)))
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*total += 1;
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return true;
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}
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/* fallthrough */
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case ASHIFT:
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case ASHIFTRT:
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case LSHIFTRT:
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case ROTATE:
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case ROTATERT:
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case AND:
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case XOR:
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case NEG:
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case NOT:
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*total = COSTS_N_INSNS (1);
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return false;
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case PLUS:
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case MINUS:
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*total = COSTS_N_INSNS (1);
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@ -3706,6 +3767,38 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
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case COMPARE:
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*total = COSTS_N_INSNS (1);
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/* nxrk, nxgrk ~(a^b)==0 */
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if (TARGET_ARCH13
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&& GET_CODE (XEXP (x, 0)) == NOT
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&& XEXP (x, 1) == const0_rtx
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&& GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
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&& (GET_MODE (XEXP (x, 0)) == SImode || GET_MODE (XEXP (x, 0)) == DImode)
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&& mode == CCZmode)
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{
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if (!REG_P (XEXP (XEXP (XEXP (x, 0), 0), 0)))
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*total += 1;
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if (!REG_P (XEXP (XEXP (XEXP (x, 0), 0), 1)))
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*total += 1;
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return true;
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}
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/* nnrk, nngrk, nork, nogrk */
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if (TARGET_ARCH13
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&& (GET_CODE (XEXP (x, 0)) == AND || GET_CODE (XEXP (x, 0)) == IOR)
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&& XEXP (x, 1) == const0_rtx
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&& (GET_MODE (XEXP (x, 0)) == SImode || GET_MODE (XEXP (x, 0)) == DImode)
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&& GET_CODE (XEXP (XEXP (x, 0), 0)) == NOT
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&& GET_CODE (XEXP (XEXP (x, 0), 1)) == NOT
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&& mode == CCZmode)
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{
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if (!REG_P (XEXP (XEXP (XEXP (x, 0), 0), 0)))
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*total += 1;
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if (!REG_P (XEXP (XEXP (XEXP (x, 0), 1), 0)))
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*total += 1;
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return true;
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}
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if (GET_CODE (XEXP (x, 0)) == AND
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&& GET_CODE (XEXP (x, 1)) == CONST_INT
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&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
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@ -669,6 +669,12 @@
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;; This iterator allows r[ox]sbg to be defined with the same template
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(define_code_iterator IXOR [ior xor])
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;; This is used for merging the nand/nor and and/or with complement patterns
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(define_code_iterator ANDOR [and ior])
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(define_code_attr bitops_name [(and "and") (ior "or")])
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(define_code_attr inv_bitops_name [(and "or") (ior "and")])
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(define_code_attr inv_no [(and "o") (ior "n")])
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;; This iterator is used to expand the patterns for the nearest
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;; integer functions.
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(define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC
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@ -7534,7 +7540,8 @@
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(and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" ""))
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(match_operand:GPR 2 "general_operand" "")))
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(clobber (reg:CC CC_REGNUM))]
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"! reload_completed
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"!TARGET_ARCH13
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&& ! reload_completed
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&& (GET_CODE (operands[0]) != MEM
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/* Ensure that s390_logical_operator_ok_p will succeed even
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on the split xor if (b & a) is stored into a pseudo. */
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@ -7876,6 +7883,87 @@
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[(set_attr "op_type" "RR,SI,SS")
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(set_attr "z10prop" "z10_super_E1,z10_super,*")])
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;
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; And/Or with complement
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;
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; ncrk, ncgrk, ocrk, ocgrk
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(define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cc"
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[(set (reg CC_REGNUM)
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(compare
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(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
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(match_operand:GPR 2 "register_operand" "d"))
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(const_int 0)))
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(set (match_operand:GPR 0 "register_operand" "=d")
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(ANDOR:GPR (not:GPR (match_dup 1))
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(match_dup 2)))]
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"TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
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"<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
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[(set_attr "op_type" "RRF")])
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; ncrk, ncgrk, ocrk, ocgrk
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(define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cconly"
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[(set (reg CC_REGNUM)
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(compare
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(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
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(match_operand:GPR 2 "register_operand" "d"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=d"))]
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"TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
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"<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
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[(set_attr "op_type" "RRF")])
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; ncrk, ncgrk, ocrk, ocgrk
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(define_insn "*<ANDOR:bitops_name>c<GPR:mode>"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
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(match_operand:GPR 2 "register_operand" "d")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_ARCH13"
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"<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1"
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[(set_attr "op_type" "RRF")])
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;
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;- Nand/Nor instructions.
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;
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; nnrk, nngrk, nork, nogrk
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(define_insn "*n<ANDOR:inv_bitops_name><GPR:mode>_cc"
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[(set (reg CC_REGNUM)
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(compare
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(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
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(not:GPR (match_operand:GPR 2 "register_operand" "d")))
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(const_int 0)))
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(set (match_operand:GPR 0 "register_operand" "=d")
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(ANDOR:GPR (not:GPR (match_dup 1))
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(not:GPR (match_dup 2))))]
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"TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
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"n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
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[(set_attr "op_type" "RRF")])
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; nnrk, nngrk, nork, nogrk
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(define_insn "*n<ANDOR:inv_bitops_name><mode>_cconly"
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[(set (reg CC_REGNUM)
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(compare
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(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
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(not:GPR (match_operand:GPR 2 "register_operand" "d")))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=d"))]
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"TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
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"n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
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[(set_attr "op_type" "RRF")])
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; nnrk, nngrk, nork, nogrk
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(define_insn "*n<ANDOR:inv_bitops_name><mode>"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
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(not:GPR (match_operand:GPR 2 "register_operand" "d"))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_ARCH13"
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"n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2"
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[(set_attr "op_type" "RRF")])
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;
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; Block inclusive or (OC) patterns.
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;
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@ -8241,6 +8329,45 @@
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"operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
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operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
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;
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;- Nxor instructions.
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;
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; nxrk, nxgrk
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(define_insn "*nxor<GPR:mode>_cc"
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[(set (reg CC_REGNUM)
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(compare
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(not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand:GPR 2 "register_operand" "d")))
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(const_int 0)))
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(set (match_operand:GPR 0 "register_operand" "=d")
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(xor:GPR (not:GPR (match_dup 1))
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(match_dup 2)))]
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"TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
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"nx<GPR:g>rk\t%0,%1,%2"
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[(set_attr "op_type" "RRF")])
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; nxrk, nxgrk
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(define_insn "*nxor<mode>_cconly"
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[(set (reg CC_REGNUM)
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(compare
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(not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand:GPR 2 "register_operand" "d")))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=d"))]
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"TARGET_ARCH13 && s390_match_ccmode(insn, CCTmode)"
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"nx<GPR:g>rk\t%0,%1,%2"
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[(set_attr "op_type" "RRF")])
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; nxrk, nxgrk
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(define_insn "*nxor<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand:GPR 2 "register_operand" "d"))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_ARCH13"
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"nx<GPR:g>rk\t%0,%1,%2"
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[(set_attr "op_type" "RRF")])
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;;
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;;- Negate instructions.
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@ -1,3 +1,11 @@
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2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
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* gcc.target/s390/arch13/bitops-1.c: New test.
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* gcc.target/s390/arch13/bitops-2.c: New test.
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* gcc.target/s390/md/andc-splitter-1.c: Add -march=z14 build
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option and adjust line numbers.
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* gcc.target/s390/md/andc-splitter-2.c: Likewise.
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2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com>
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* gcc.target/s390/s390.exp: Run tests in arch13 subdir.
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91
gcc/testsuite/gcc.target/s390/arch13/bitops-1.c
Normal file
91
gcc/testsuite/gcc.target/s390/arch13/bitops-1.c
Normal file
@ -0,0 +1,91 @@
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/* { dg-compile } */
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/* and with complement */
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int
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ncrk (int a, int b)
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{
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return a & ~b;
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}
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/* { dg-final { scan-assembler-times "\tncrk\t" 1 } } */
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long long
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ncgrk (long long a, long long b)
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{
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return a & ~b;
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}
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/* { dg-final { scan-assembler-times "\tncgrk\t" 1 } } */
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/* or with complement */
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int
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ocrk (int a, int b)
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{
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return a | ~b;
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}
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/* { dg-final { scan-assembler-times "\tocrk\t" 1 } } */
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long long
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ocgrk (long long a, long long b)
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{
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return a | ~b;
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}
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/* { dg-final { scan-assembler-times "\tocgrk\t" 1 } } */
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/* nand */
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int
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nnrk (int a, int b)
|
||||
{
|
||||
return ~(a & b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnnrk\t" 1 } } */
|
||||
|
||||
long long
|
||||
nngrk (long long a, long long b)
|
||||
{
|
||||
return ~(a & b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnngrk\t" 1 } } */
|
||||
|
||||
/* nor */
|
||||
|
||||
int
|
||||
nork (int a, int b)
|
||||
{
|
||||
return ~(a | b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnork\t" 1 } } */
|
||||
|
||||
long long
|
||||
nogrk (long long a, long long b)
|
||||
{
|
||||
return ~(a | b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnogrk\t" 1 } } */
|
||||
|
||||
/* nxor */
|
||||
|
||||
int
|
||||
nxrk (int a, int b)
|
||||
{
|
||||
return ~(a ^ b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnxrk\t" 1 } } */
|
||||
|
||||
long long
|
||||
nxgrk (long long a, long long b)
|
||||
{
|
||||
return ~(a ^ b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnxgrk\t" 1 } } */
|
||||
93
gcc/testsuite/gcc.target/s390/arch13/bitops-2.c
Normal file
93
gcc/testsuite/gcc.target/s390/arch13/bitops-2.c
Normal file
@ -0,0 +1,93 @@
|
||||
/* { dg-compile } */
|
||||
|
||||
/* Check if the instruction are being used also for compares. */
|
||||
|
||||
/* and with complement */
|
||||
|
||||
int
|
||||
ncrk (int a, int b)
|
||||
{
|
||||
return (a & ~b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tncrk\t" 1 } } */
|
||||
|
||||
int
|
||||
ncgrk (long long a, long long b)
|
||||
{
|
||||
return (a & ~b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tncgrk\t" 1 } } */
|
||||
|
||||
/* or with complement */
|
||||
|
||||
int
|
||||
ocrk (int a, int b)
|
||||
{
|
||||
return (a | ~b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tocrk\t" 1 } } */
|
||||
|
||||
int
|
||||
ocgrk (long long a, long long b)
|
||||
{
|
||||
return (a | ~b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tocgrk\t" 1 } } */
|
||||
|
||||
/* nand */
|
||||
|
||||
int
|
||||
nnrk (int a, int b)
|
||||
{
|
||||
return ~(a & b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnnrk\t" 1 } } */
|
||||
|
||||
int
|
||||
nngrk (long long a, long long b)
|
||||
{
|
||||
return ~(a & b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnngrk\t" 1 } } */
|
||||
|
||||
/* nor */
|
||||
|
||||
int
|
||||
nork (int a, int b)
|
||||
{
|
||||
return ~(a | b);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnork\t" 1 } } */
|
||||
|
||||
int
|
||||
nogrk (long long a, long long b)
|
||||
{
|
||||
return ~(a | b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnogrk\t" 1 } } */
|
||||
|
||||
/* nxor */
|
||||
|
||||
int
|
||||
nxrk (int a, int b)
|
||||
{
|
||||
return ~(a ^ b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnxrk\t" 1 } } */
|
||||
|
||||
int
|
||||
nxgrk (long long a, long long b)
|
||||
{
|
||||
return ~(a ^ b) ? 23 : 42;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnxgrk\t" 1 } } */
|
||||
@ -1,7 +1,9 @@
|
||||
/* Machine description pattern tests. */
|
||||
|
||||
/* { dg-do compile { target { lp64 } } } */
|
||||
/* { dg-options "-mzarch -save-temps -dP" } */
|
||||
/* Starting with arch13 the and with complement instruction is
|
||||
available and the splitter is disabled. */
|
||||
/* { dg-options "-march=z14 -mzarch -save-temps -dP" } */
|
||||
/* { dg-do run { target { lp64 && s390_useable_hw } } } */
|
||||
/* Skip test if -O0 is present on the command line:
|
||||
|
||||
@ -14,26 +16,26 @@
|
||||
__attribute__ ((noinline))
|
||||
unsigned long andc_vv(unsigned long a, unsigned long b)
|
||||
{ return ~b & a; }
|
||||
/* { dg-final { scan-assembler ":16:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":16:.\* \{\\*xordi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":18:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":18:.\* \{\\*xordi3\}" } } */
|
||||
|
||||
__attribute__ ((noinline))
|
||||
unsigned long andc_pv(unsigned long *a, unsigned long b)
|
||||
{ return ~b & *a; }
|
||||
/* { dg-final { scan-assembler ":22:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":22:.\* \{\\*xordi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":24:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":24:.\* \{\\*xordi3\}" } } */
|
||||
|
||||
__attribute__ ((noinline))
|
||||
unsigned long andc_vp(unsigned long a, unsigned long *b)
|
||||
{ return ~*b & a; }
|
||||
/* { dg-final { scan-assembler ":28:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":28:.\* \{\\*xordi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":30:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":30:.\* \{\\*xordi3\}" } } */
|
||||
|
||||
__attribute__ ((noinline))
|
||||
unsigned long andc_pp(unsigned long *a, unsigned long *b)
|
||||
{ return ~*b & *a; }
|
||||
/* { dg-final { scan-assembler ":34:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":34:.\* \{\\*xordi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":36:.\* \{\\*anddi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":36:.\* \{\\*xordi3\}" } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tngr\?k\?\t" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "\txgr\?\t" 4 } } */
|
||||
|
||||
@ -1,7 +1,9 @@
|
||||
/* Machine description pattern tests. */
|
||||
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-save-temps -dP" } */
|
||||
/* Starting with arch13 the and with complement instruction is
|
||||
available and the splitter is disabled. */
|
||||
/* { dg-options "-march=z14 -save-temps -dP" } */
|
||||
/* { dg-do run { target { s390_useable_hw } } } */
|
||||
/* Skip test if -O0 is present on the command line:
|
||||
|
||||
@ -14,26 +16,26 @@
|
||||
__attribute__ ((noinline))
|
||||
unsigned int andc_vv(unsigned int a, unsigned int b)
|
||||
{ return ~b & a; }
|
||||
/* { dg-final { scan-assembler ":16:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":16:.\* \{\\*xorsi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":18:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":18:.\* \{\\*xorsi3\}" } } */
|
||||
|
||||
__attribute__ ((noinline))
|
||||
unsigned int andc_pv(unsigned int *a, unsigned int b)
|
||||
{ return ~b & *a; }
|
||||
/* { dg-final { scan-assembler ":22:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":22:.\* \{\\*xorsi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":24:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":24:.\* \{\\*xorsi3\}" } } */
|
||||
|
||||
__attribute__ ((noinline))
|
||||
unsigned int andc_vp(unsigned int a, unsigned int *b)
|
||||
{ return ~*b & a; }
|
||||
/* { dg-final { scan-assembler ":28:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":28:.\* \{\\*xorsi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":30:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":30:.\* \{\\*xorsi3\}" } } */
|
||||
|
||||
__attribute__ ((noinline))
|
||||
unsigned int andc_pp(unsigned int *a, unsigned int *b)
|
||||
{ return ~*b & *a; }
|
||||
/* { dg-final { scan-assembler ":34:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":34:.\* \{\\*xorsi3\}" } } */
|
||||
/* { dg-final { scan-assembler ":36:.\* \{\\*andsi3_\(esa\|zarch\)\}" } } */
|
||||
/* { dg-final { scan-assembler ":36:.\* \{\\*xorsi3\}" } } */
|
||||
|
||||
/* { dg-final { scan-assembler-times "\tnr\?k\?\t" 4 } } */
|
||||
/* { dg-final { scan-assembler-times "\txr\?k\?\t" 4 } } */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user