re PR target/78904 (zero-extracts are not effective)
PR target/78904 * config/i386/constraints.md (Bc): New special memory constraint. * config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use Bc constraint with nonimmediate_operand to allow constant memory operands. (*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1) (*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use Bc constraint with general_operand to allow constant memory operands. testsuite/ChangeLog: PR target/78904 * gcc.target/i386/pr78904-3.c: New test. From-SVN: r243937
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
8ba4f50639
commit
4b6d0c0eb4
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@ -1,3 +1,13 @@
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2016-12-27 Uros Bizjak <ubizjak@gmail.com>
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PR target/78904
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* config/i386/constraints.md (Bc): New special memory constraint.
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* config/i386/i386.md (*cmpqi_ext_1, *extvqi, *extzvqi): Use Bc
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constraint with nonimmediate_operand to allow constant memory operands.
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(*cmpqi_ext_3, insv<mode>_1, addqi_ext_1, *testqi_ext_1, andqi_ext_1)
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(*<any_or:code>qi_ext_1, *xorqi_ext_1_cc): Use Bc constraint
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with general_operand to allow constant memory operands.
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2016-12-27 Alexander Ivchenko <alexander.ivchenko@intel.com>
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* c-family/c.opt (flag_chkp_flexible_struct_trailing_arrays):
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@ -168,6 +168,7 @@
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;; f FLAGS_REG
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;; g GOT memory operand.
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;; m Vector memory operand
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;; c Constant memory operand
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;; s Sibcall memory operand, not valid for TARGET_X32
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;; w Call memory operand, not valid for TARGET_X32
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;; z Constant call address operand.
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@ -185,6 +186,11 @@
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"@internal Vector memory operand."
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(match_operand 0 "vector_memory_operand"))
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(define_special_memory_constraint "Bc"
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"@internal Constant memory operand."
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(and (match_operand 0 "memory_operand")
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(match_test "constant_address_p (XEXP (op, 0))")))
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(define_constraint "Bs"
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"@internal Sibcall memory operand."
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(ior (and (not (match_test "TARGET_X32"))
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@ -1295,7 +1295,7 @@
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(define_insn "*cmpqi_ext_1"
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[(set (reg FLAGS_REG)
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(compare
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(match_operand:QI 0 "nonimmediate_operand" "Q,m")
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(match_operand:QI 0 "nonimmediate_operand" "QBc,m")
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(subreg:QI
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(zero_extract:SI
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(match_operand 1 "ext_register_operand" "Q,Q")
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@ -1340,7 +1340,7 @@
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(match_operand 0 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "general_operand" "Qn,m")))]
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(match_operand:QI 1 "general_operand" "QnBc,m")))]
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"ix86_match_ccmode (insn, CCmode)"
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"cmp{b}\t{%1, %h0|%h0, %1}"
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[(set_attr "isa" "*,nox64")
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@ -2781,7 +2781,7 @@
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(set_attr "mode" "SI")])
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(define_insn "*extvqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
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(sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q,Q")
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(const_int 8)
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(const_int 8)))]
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@ -2836,7 +2836,7 @@
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(set_attr "mode" "SI")])
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(define_insn "*extzvqi"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=Q,?R,m")
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[(set (match_operand:QI 0 "nonimmediate_operand" "=QBc,?R,m")
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(subreg:QI
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(zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q,Q")
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(const_int 8)
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@ -2897,7 +2897,7 @@
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[(set (zero_extract:SWI248 (match_operand 0 "ext_register_operand" "+Q,Q")
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(const_int 8)
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(const_int 8))
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(match_operand:SWI248 1 "general_operand" "Qn,m"))]
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(match_operand:SWI248 1 "general_operand" "QnBc,m"))]
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""
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{
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if (CONST_INT_P (operands[1]))
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@ -6087,7 +6087,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_operand" "Qn,m")) 0))
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(match_operand:QI 2 "general_operand" "QnBc,m")) 0))
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(clobber (reg:CC FLAGS_REG))]
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""
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{
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@ -7889,7 +7889,7 @@
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(zero_extract:SI (match_operand 0 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "general_operand" "Qn,m"))
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(match_operand:QI 1 "general_operand" "QnBc,m"))
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(const_int 0)))]
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"ix86_match_ccmode (insn, CCNOmode)"
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"test{b}\t{%1, %h0|%h0, %1}"
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@ -8417,7 +8417,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_operand" "Qn,m")) 0))
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(match_operand:QI 2 "general_operand" "QnBc,m")) 0))
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(clobber (reg:CC FLAGS_REG))]
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""
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"and{b}\t{%2, %h0|%h0, %2}"
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@ -8435,7 +8435,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_operand" "Qn,m"))
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(match_operand:QI 2 "general_operand" "QnBc,m"))
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(const_int 0)))
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(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q")
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(const_int 8)
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@ -8804,7 +8804,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_operand" "Qn,m")) 0))
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(match_operand:QI 2 "general_operand" "QnBc,m")) 0))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"<logic>{b}\t{%2, %h0|%h0, %2}"
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@ -8914,7 +8914,7 @@
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(zero_extract:SI (match_operand 1 "ext_register_operand" "0,0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "general_operand" "Qn,m"))
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(match_operand:QI 2 "general_operand" "QnBc,m"))
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(const_int 0)))
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(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q,Q")
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(const_int 8)
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@ -1,3 +1,8 @@
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2016-12-27 Uros Bizjak <ubizjak@gmail.com>
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PR target/78904
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* gcc.target/i386/pr78904-3.c: New test.
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2016-12-27 Alexander Ivchenko <alexander.ivchenko@intel.com>
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* gcc.target/i386/mpx/vla-trailing-1-lbv.c: New test.
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@ -0,0 +1,42 @@
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/* PR target/78904 */
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/* { dg-do assemble } */
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/* { dg-options "-O2" } */
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typedef __SIZE_TYPE__ size_t;
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struct S1
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{
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unsigned char pad1;
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unsigned char val;
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unsigned short pad2;
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};
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extern struct S1 t[256];
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struct S1 test_and (struct S1 a, size_t i)
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{
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a.val &= t[i].val;
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return a;
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}
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struct S1 test_or (struct S1 a, size_t i)
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{
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a.val |= t[i].val;
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return a;
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}
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struct S1 test_xor (struct S1 a, size_t i)
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{
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a.val ^= t[i].val;
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return a;
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}
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struct S1 test_add (struct S1 a, size_t i)
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{
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a.val += t[i].val;
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return a;
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}
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