[ARM] PR68532: Fix up vuzp for big endian
gcc/ChangeLog:
2016-02-09 Charles Baylis <charles.baylis@linaro.org>
PR target/68532
* config/arm/arm.c (neon_endian_lane_map): New function.
(neon_vector_pair_endian_lane_map): New function.
(arm_evpc_neon_vuzp): Allow for big endian lane order.
* config/arm/arm_neon.h (vuzpq_s8): Adjust shuffle patterns for big
endian.
(vuzpq_s16): Likewise.
(vuzpq_s32): Likewise.
(vuzpq_f32): Likewise.
(vuzpq_u8): Likewise.
(vuzpq_u16): Likewise.
(vuzpq_u32): Likewise.
(vuzpq_p8): Likewise.
(vuzpq_p16): Likewise.
gcc/testsuite/ChangeLog:
2016-02-09 Charles Baylis <charles.baylis@linaro.org>
PR target/68532
* gcc.c-torture/execute/pr68532.c: New test.
From-SVN: r233251
This commit is contained in:
Charles Baylis
Charles Baylis
parent
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commit
4b79ac23c6
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@ -1,3 +1,20 @@
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2016-02-09 Charles Baylis <charles.baylis@linaro.org>
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PR target/68532
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* config/arm/arm.c (neon_endian_lane_map): New function.
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(neon_vector_pair_endian_lane_map): New function.
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(arm_evpc_neon_vuzp): Allow for big endian lane order.
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* config/arm/arm_neon.h (vuzpq_s8): Adjust shuffle patterns for big
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endian.
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(vuzpq_s16): Likewise.
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(vuzpq_s32): Likewise.
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(vuzpq_f32): Likewise.
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(vuzpq_u8): Likewise.
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(vuzpq_u16): Likewise.
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(vuzpq_u32): Likewise.
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(vuzpq_p8): Likewise.
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(vuzpq_p16): Likewise.
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2016-02-11 Alexandre Oliva <aoliva@redhat.com>
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PR target/69634
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@ -28203,6 +28203,37 @@ arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
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arm_expand_vec_perm_1 (target, op0, op1, sel);
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}
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/* Map lane ordering between architectural lane order, and GCC lane order,
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taking into account ABI. See comment above output_move_neon for details. */
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static int
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neon_endian_lane_map (machine_mode mode, int lane)
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{
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if (BYTES_BIG_ENDIAN)
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{
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int nelems = GET_MODE_NUNITS (mode);
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/* Reverse lane order. */
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lane = (nelems - 1 - lane);
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/* Reverse D register order, to match ABI. */
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if (GET_MODE_SIZE (mode) == 16)
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lane = lane ^ (nelems / 2);
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}
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return lane;
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}
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/* Some permutations index into pairs of vectors, this is a helper function
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to map indexes into those pairs of vectors. */
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static int
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neon_pair_endian_lane_map (machine_mode mode, int lane)
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{
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int nelem = GET_MODE_NUNITS (mode);
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if (BYTES_BIG_ENDIAN)
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lane =
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neon_endian_lane_map (mode, lane & (nelem - 1)) + (lane & nelem);
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return lane;
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}
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/* Generate or test for an insn that supports a constant permutation. */
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/* Recognize patterns for the VUZP insns. */
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@ -28213,14 +28244,22 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
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unsigned int i, odd, mask, nelt = d->nelt;
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rtx out0, out1, in0, in1;
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rtx (*gen)(rtx, rtx, rtx, rtx);
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int first_elem;
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int swap_nelt;
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if (GET_MODE_UNIT_SIZE (d->vmode) >= 8)
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return false;
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/* Note that these are little-endian tests. Adjust for big-endian later. */
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if (d->perm[0] == 0)
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/* arm_expand_vec_perm_const_1 () helpfully swaps the operands for the
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big endian pattern on 64 bit vectors, so we correct for that. */
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swap_nelt = BYTES_BIG_ENDIAN && !d->one_vector_p
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&& GET_MODE_SIZE (d->vmode) == 8 ? d->nelt : 0;
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first_elem = d->perm[neon_endian_lane_map (d->vmode, 0)] ^ swap_nelt;
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if (first_elem == neon_endian_lane_map (d->vmode, 0))
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odd = 0;
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else if (d->perm[0] == 1)
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else if (first_elem == neon_endian_lane_map (d->vmode, 1))
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odd = 1;
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else
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return false;
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@ -28228,8 +28267,9 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
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for (i = 0; i < nelt; i++)
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{
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unsigned elt = (i * 2 + odd) & mask;
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if (d->perm[i] != elt)
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unsigned elt =
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(neon_pair_endian_lane_map (d->vmode, i) * 2 + odd) & mask;
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if ((d->perm[i] ^ swap_nelt) != neon_pair_endian_lane_map (d->vmode, elt))
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return false;
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}
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@ -28253,11 +28293,8 @@ arm_evpc_neon_vuzp (struct expand_vec_perm_d *d)
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in0 = d->op0;
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in1 = d->op1;
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if (BYTES_BIG_ENDIAN)
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{
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std::swap (in0, in1);
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odd = !odd;
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}
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if (swap_nelt != 0)
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std::swap (in0, in1);
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out0 = d->target;
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out1 = gen_reg_rtx (d->vmode);
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@ -8741,9 +8741,9 @@ vuzpq_s8 (int8x16_t __a, int8x16_t __b)
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int8x16x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15 });
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{ 9, 11, 13, 15, 1, 3, 5, 7, 25, 27, 29, 31, 17, 19, 21, 23 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14 });
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{ 8, 10, 12, 14, 0, 2, 4, 6, 24, 26, 28, 30, 16, 18, 20, 22 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 });
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@ -8759,9 +8759,9 @@ vuzpq_s16 (int16x8_t __a, int16x8_t __b)
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int16x8x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 9, 11, 13, 15, 1, 3, 5, 7 });
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{ 5, 7, 1, 3, 13, 15, 9, 11 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 8, 10, 12, 14, 0, 2, 4, 6 });
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{ 4, 6, 0, 2, 12, 14, 8, 10 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 0, 2, 4, 6, 8, 10, 12, 14 });
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@ -8776,8 +8776,8 @@ vuzpq_s32 (int32x4_t __a, int32x4_t __b)
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{
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int32x4x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 5, 7, 1, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 4, 6, 0, 2 });
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 3, 1, 7, 5 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 2, 0, 6, 4 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 0, 2, 4, 6 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 1, 3, 5, 7 });
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@ -8790,8 +8790,8 @@ vuzpq_f32 (float32x4_t __a, float32x4_t __b)
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{
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float32x4x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 5, 7, 1, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 4, 6, 0, 2 });
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 3, 1, 7, 5 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 2, 0, 6, 4 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 0, 2, 4, 6 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 1, 3, 5, 7 });
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@ -8805,9 +8805,9 @@ vuzpq_u8 (uint8x16_t __a, uint8x16_t __b)
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uint8x16x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15 });
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{ 9, 11, 13, 15, 1, 3, 5, 7, 25, 27, 29, 31, 17, 19, 21, 23 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14 });
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{ 8, 10, 12, 14, 0, 2, 4, 6, 24, 26, 28, 30, 16, 18, 20, 22 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 });
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@ -8823,9 +8823,9 @@ vuzpq_u16 (uint16x8_t __a, uint16x8_t __b)
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uint16x8x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 9, 11, 13, 15, 1, 3, 5, 7 });
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{ 5, 7, 1, 3, 13, 15, 9, 11 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 8, 10, 12, 14, 0, 2, 4, 6 });
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{ 4, 6, 0, 2, 12, 14, 8, 10 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 0, 2, 4, 6, 8, 10, 12, 14 });
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@ -8840,8 +8840,8 @@ vuzpq_u32 (uint32x4_t __a, uint32x4_t __b)
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{
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uint32x4x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 5, 7, 1, 3 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 4, 6, 0, 2 });
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 3, 1, 7, 5 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 2, 0, 6, 4 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint32x4_t) { 0, 2, 4, 6 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint32x4_t) { 1, 3, 5, 7 });
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@ -8855,9 +8855,9 @@ vuzpq_p8 (poly8x16_t __a, poly8x16_t __b)
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poly8x16x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 17, 19, 21, 23, 25, 27, 29, 31, 1, 3, 5, 7, 9, 11, 13, 15 });
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{ 9, 11, 13, 15, 1, 3, 5, 7, 25, 27, 29, 31, 17, 19, 21, 23 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 16, 18, 20, 22, 24, 26, 28, 30, 0, 2, 4, 6, 8, 10, 12, 14 });
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{ 8, 10, 12, 14, 0, 2, 4, 6, 24, 26, 28, 30, 16, 18, 20, 22 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint8x16_t)
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{ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 });
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@ -8873,9 +8873,9 @@ vuzpq_p16 (poly16x8_t __a, poly16x8_t __b)
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poly16x8x2_t __rv;
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#ifdef __ARM_BIG_ENDIAN
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 9, 11, 13, 15, 1, 3, 5, 7 });
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{ 5, 7, 1, 3, 13, 15, 9, 11 });
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__rv.val[1] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 8, 10, 12, 14, 0, 2, 4, 6 });
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{ 4, 6, 0, 2, 12, 14, 8, 10 });
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#else
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__rv.val[0] = __builtin_shuffle (__a, __b, (uint16x8_t)
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{ 0, 2, 4, 6, 8, 10, 12, 14 });
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@ -1,3 +1,8 @@
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2016-02-09 Charles Baylis <charles.baylis@linaro.org>
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PR target/68532
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* gcc.c-torture/execute/pr68532.c: New test.
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2016-02-11 Alexandre Oliva <aoliva@redhat.com>
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PR target/69634
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@ -0,0 +1,22 @@
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/* { dg-options "-O2 -ftree-vectorize -fno-vect-cost-model" } */
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#define SIZE 128
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unsigned short _Alignas (16) in[SIZE];
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__attribute__ ((noinline)) int
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test (unsigned short sum, unsigned short *in, int x)
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{
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for (int j = 0; j < SIZE; j += 8)
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sum += in[j] * x;
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return sum;
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}
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int
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main ()
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{
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for (int i = 0; i < SIZE; i++)
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in[i] = i;
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if (test (0, in, 1) != 960)
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__builtin_abort ();
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return 0;
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}
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