m32r.h (REG_OK_FOR_BASE_P, [...]): Remove macros.
* config/m32r/m32r.h (REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P, RTX_OK_FOR_BASE_P, RTX_OK_FOR_OFFSET_P, LEGITIMATE_OFFSET_ADDRESS_P, LEGITIMATE_LO_SUM_ADDRESS_P, LOAD_POSTINC_P, STORE_PREINC_PREDEC_P, GO_IF_LEGITIMATE_ADDRESS): Remove macros. * config/m32r/m32r.c (TARGET_LEGITIMATE_ADDRESS_P): Define. (m32r_rtx_ok_for_base_p, m32r_rtx_ok_for_offset_p, m32r_legitimate_offset_addres_p, m32r_legitimate_lo_sum_addres_p, m32r_load_postinc_p, m32r_store_preinc_predec_p, m32r_legitimate_address_p): New functions. * config/m32r/constraints.md (constraint "S"): Don't use STORE_PREINC_PREDEC_P. (constraint "U"): Don't use LOAD_POSTINC_P. From-SVN: r170278
This commit is contained in:
Anatoly Sokolov
Anatoly Sokolov
parent
7efcf910ee
commit
4bf7ff7ebd
@ -1,3 +1,18 @@
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2011-02-18 Anatoly Sokolov <aesok@post.ru>
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* config/m32r/m32r.h (REG_OK_FOR_BASE_P, REG_OK_FOR_INDEX_P,
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RTX_OK_FOR_BASE_P, RTX_OK_FOR_OFFSET_P, LEGITIMATE_OFFSET_ADDRESS_P,
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LEGITIMATE_LO_SUM_ADDRESS_P, LOAD_POSTINC_P, STORE_PREINC_PREDEC_P,
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GO_IF_LEGITIMATE_ADDRESS): Remove macros.
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* config/m32r/m32r.c (TARGET_LEGITIMATE_ADDRESS_P): Define.
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(m32r_rtx_ok_for_base_p, m32r_rtx_ok_for_offset_p,
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m32r_legitimate_offset_addres_p, m32r_legitimate_lo_sum_addres_p,
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m32r_load_postinc_p, m32r_store_preinc_predec_p,
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m32r_legitimate_address_p): New functions.
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* config/m32r/constraints.md (constraint "S"): Don't use
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STORE_PREINC_PREDEC_P.
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(constraint "U"): Don't use LOAD_POSTINC_P.
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2011-02-18 Chung-Lin Tang <cltang@codesourcery.com>
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PR rtl-optimization/46178
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@ -1,5 +1,5 @@
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;; Constraint definitions for Renesas M32R cpu for GNU C compiler
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;; Copyright (C) 2007, 2011 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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@ -118,7 +118,12 @@
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(define_constraint "S"
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"A store with pre {inc,dec}rement."
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(and (match_code "mem")
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(match_test "STORE_PREINC_PREDEC_P (GET_MODE (op), XEXP (op, 0))")))
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(match_test "mode == SImode || mode == SFmode")
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(match_code "pre_inc,pre_dec" "0")
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(match_code "reg" "00")
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(match_test "GPR_P (REGNO (XEXP (XEXP (op, 0), 0)))
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|| REGNO (XEXP (XEXP (op, 0), 0)) == ARG_POINTER_REGNUM
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|| ! HARD_REGISTER_P (XEXP (XEXP (op, 0), 0))")))
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(define_constraint "T"
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"An indirect of a pointer."
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@ -128,7 +133,12 @@
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(define_constraint "U"
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"A load with post increment."
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(and (match_code "mem")
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(match_test "LOAD_POSTINC_P (GET_MODE (op), XEXP (op, 0))")))
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(match_test "mode == SImode || mode == SFmode")
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(match_code "post_inc" "0")
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(match_code "reg" "00")
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(match_test "GPR_P (REGNO (XEXP (XEXP (op, 0), 0)))
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|| REGNO (XEXP (XEXP (op, 0), 0)) == ARG_POINTER_REGNUM
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|| ! HARD_REGISTER_P (XEXP (XEXP (op, 0), 0))")))
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(define_constraint "W"
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"zero immediate."
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@ -66,6 +66,7 @@ static void m32r_option_override (void);
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static void init_reg_tables (void);
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static void block_move_call (rtx, rtx, rtx);
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static int m32r_is_insn (rtx);
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static bool m32r_legitimate_address_p (enum machine_mode, rtx, bool);
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static rtx m32r_legitimize_address (rtx, rtx, enum machine_mode);
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static bool m32r_mode_dependent_address_p (const_rtx);
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static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
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@ -124,6 +125,8 @@ static const struct default_options m32r_option_optimization_table[] =
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#undef TARGET_ATTRIBUTE_TABLE
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#define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
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#undef TARGET_LEGITIMATE_ADDRESS_P
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#define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
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#undef TARGET_LEGITIMIZE_ADDRESS
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#define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
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#undef TARGET_MODE_DEPENDENT_ADDRESS_P
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@ -2844,6 +2847,107 @@ m32r_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
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GEN_INT (3), SImode);
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}
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/* True if X is a reg that can be used as a base reg. */
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static bool
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m32r_rtx_ok_for_base_p (const_rtx x, bool strict)
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{
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if (! REG_P (x))
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return false;
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if (strict)
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{
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if (GPR_P (REGNO (x)))
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return true;
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}
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else
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{
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if (GPR_P (REGNO (x))
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|| REGNO (x) == ARG_POINTER_REGNUM
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|| ! HARD_REGISTER_P (x))
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return true;
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}
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return false;
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}
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static inline bool
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m32r_rtx_ok_for_offset_p (const_rtx x)
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{
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return (CONST_INT_P (x) && INT16_P (INTVAL (x)));
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}
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static inline bool
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m32r_legitimate_offset_addres_p (enum machine_mode mode ATTRIBUTE_UNUSED,
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const_rtx x, bool strict)
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{
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if (GET_CODE (x) == PLUS
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&& m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
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&& m32r_rtx_ok_for_offset_p (XEXP (x, 1)))
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return true;
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return false;
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}
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/* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
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since more than one instruction will be required. */
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static inline bool
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m32r_legitimate_lo_sum_addres_p (enum machine_mode mode, const_rtx x,
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bool strict)
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{
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if (GET_CODE (x) == LO_SUM
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&& (mode != BLKmode && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
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&& m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)
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&& CONSTANT_P (XEXP (x, 1)))
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return true;
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return false;
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}
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/* Is this a load and increment operation. */
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static inline bool
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m32r_load_postinc_p (enum machine_mode mode, const_rtx x, bool strict)
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{
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if ((mode == SImode || mode == SFmode)
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&& GET_CODE (x) == POST_INC
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&& REG_P (XEXP (x, 0))
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&& m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
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return true;
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return false;
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}
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/* Is this an increment/decrement and store operation. */
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static inline bool
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m32r_store_preinc_predec_p (enum machine_mode mode, const_rtx x, bool strict)
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{
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if ((mode == SImode || mode == SFmode)
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&& (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
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&& REG_P (XEXP (x, 0)) \
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&& m32r_rtx_ok_for_base_p (XEXP (x, 0), strict))
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return true;
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return false;
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}
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/* Implement TARGET_LEGITIMATE_ADDRESS_P. */
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static bool
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m32r_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
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{
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if (m32r_rtx_ok_for_base_p (x, strict)
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|| m32r_legitimate_offset_addres_p (mode, x, strict)
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|| m32r_legitimate_lo_sum_addres_p (mode, x, strict)
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|| m32r_load_postinc_p (mode, x, strict)
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|| m32r_store_preinc_predec_p (mode, x, strict))
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return true;
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return false;
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}
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static void
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m32r_conditional_register_usage (void)
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{
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@ -1,6 +1,6 @@
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/* Definitions of target machine for GNU compiler, Renesas M32R cpu.
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Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
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2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
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This file is part of GCC.
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@ -858,99 +858,6 @@ L2: .word STATIC
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&& (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \
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&& CONST_INT_P (XEXP (XEXP (X, 0), 1)) \
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&& (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767))
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/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
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and check its validity for a certain class.
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We have two alternate definitions for each of them.
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The usual definition accepts all pseudo regs; the other rejects
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them unless they have been allocated suitable hard regs.
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The symbol REG_OK_STRICT causes the latter definition to be used.
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Most source files want to accept pseudo regs in the hope that
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they will get allocated to the class that the insn wants them to be in.
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Source files for reload pass need to be strict.
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After reload, it makes no difference, since pseudo regs have
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been eliminated by then. */
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#ifdef REG_OK_STRICT
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/* Nonzero if X is a hard reg that can be used as a base reg. */
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#define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X))
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/* Nonzero if X is a hard reg that can be used as an index. */
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#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
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#else
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/* Nonzero if X is a hard reg that can be used as a base reg
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or if it is a pseudo reg. */
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#define REG_OK_FOR_BASE_P(X) \
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(GPR_P (REGNO (X)) \
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|| (REGNO (X)) == ARG_POINTER_REGNUM \
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|| REGNO (X) >= FIRST_PSEUDO_REGISTER)
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/* Nonzero if X is a hard reg that can be used as an index
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or if it is a pseudo reg. */
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#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
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#endif
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/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
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that is a valid memory address for an instruction.
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The MODE argument is the machine mode for the MEM expression
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that wants to use this address. */
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/* Local to this file. */
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#define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X))
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/* Local to this file. */
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#define RTX_OK_FOR_OFFSET_P(X) \
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(CONST_INT_P (X) && INT16_P (INTVAL (X)))
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/* Local to this file. */
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#define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
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(GET_CODE (X) == PLUS \
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&& RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
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&& RTX_OK_FOR_OFFSET_P (XEXP (X, 1)))
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/* Local to this file. */
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/* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
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since more than one instruction will be required. */
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#define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \
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(GET_CODE (X) == LO_SUM \
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&& (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\
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&& RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
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&& CONSTANT_P (XEXP (X, 1)))
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/* Local to this file. */
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/* Is this a load and increment operation. */
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#define LOAD_POSTINC_P(MODE, X) \
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(((MODE) == SImode || (MODE) == SFmode) \
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&& GET_CODE (X) == POST_INC \
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&& REG_P (XEXP (X, 0)) \
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&& RTX_OK_FOR_BASE_P (XEXP (X, 0)))
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/* Local to this file. */
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/* Is this an increment/decrement and store operation. */
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#define STORE_PREINC_PREDEC_P(MODE, X) \
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(((MODE) == SImode || (MODE) == SFmode) \
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&& (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \
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&& REG_P (XEXP (X, 0)) \
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&& RTX_OK_FOR_BASE_P (XEXP (X, 0)))
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#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
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do \
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{ \
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if (RTX_OK_FOR_BASE_P (X)) \
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goto ADDR; \
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if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
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goto ADDR; \
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if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \
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goto ADDR; \
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if (LOAD_POSTINC_P ((MODE), (X))) \
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goto ADDR; \
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if (STORE_PREINC_PREDEC_P ((MODE), (X))) \
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goto ADDR; \
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} \
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while (0)
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/* Condition code usage. */
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