ns32k update from Ian Dall and Hans-Peter Nilsson.
Co-Authored-By: Hans-Peter Nilsson <hp@bitrange.com> From-SVN: r31648
This commit is contained in:
Ian Dall
Richard Henderson
parent
f85cedde61
commit
4c54e4e417
@ -1,3 +1,51 @@
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2000-01-27 Ian Dall <ian@sibyl.beware.dropbear.id.au>
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Hans-Peter Nilsson <hp@bitrange.com>
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* ns32k/xm-ns32k.h (memcpy, memset, memcmp): Delete.
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Remove redundant include of xm-ns32k.h.
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* ns32k/xm-genix.h (memcpy, memset, memcmp): Add definitions.
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Remove redundant include of xm-ns32k.h.
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* ns32k/xm-netbsd.h (memcpy, memset, memcmp): No longer undefine.
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Remove redundant include of xm-ns32k.h.
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* ns32k/netbsd.h (TARGET_DEFAULT): Enable multiply-add instructions.
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* ns32k/ns32k.h: Update comment on multiply-add instructions.
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(TARGET_SWITCHES): Add documentation strings.
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(DWARF_FRAME_REGNUM): Override default definition.
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(REG_CLASS_CONTENTS): Add comments.
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(SUBSET_P): Format to reduce line length.
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(SMALL_REGISTER_CLASSES): Make a run time option.
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(GO_IF_NONINDEXED_ADDRESS): Reformat.
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(GO_IF_LEGITIMATE_ADDRESS): Ensure that cfun is non NULL before
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dereferencing it. Braces to avoid "ambiguous else" were misplaced.
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(regclass_map): fix typo in comment.
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* ns32k/ns32k.c: Add spaces before parentheses for consistant style.
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Prefer gen_rtx_FOO(...) to gen_rtx(FOO,...).
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(trace, reg_or_mem_operand): Delete, unused function.
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(calc_address_cost): Small offsets are cheaper than large ones.
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(expand_block_move): Generate more efficient code when bytes is a
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known at compile time.
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* ns32k/ns32k.md: Alternate constraints for multiply-add instructions.
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(udivmodsi4, udivmodhi4, udivmodqi4): Use nonimmediate_operand
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instead of reg_or_mem_operand. Use VOIDmode for load or push
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effective address.
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* ns32k/ns32k.md: Use nonimmediate_operand or stricter for outputs,
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not general_operand. Similarly use "=rm" or stricter, not "=g".
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For input operands, use stricter constraints than "g" if not
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general_operand. Similarly use stricter predicate than
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"general_operand" when stricter constraints than "g" are present,
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except for matching constraints.
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(movstrsi): Use "memory_operand" for operands 0 and 1.
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(truncsiqi2, truncsihi2, trunchiqi2): Remove.
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(udivmoddisi4_internal): Use nonimmediate_operand for operand 0,
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not reg_or_mem_operand.
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(udivmoddisi4): Ditto.
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Use nonimmediate_operand for operand 1, not reg_or_mem_operand.
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Use nonimmediate_operand for operand 3, not register_operand.
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(udivmoddiqi4_internal): Use register_operand for operand 1, not
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reg_or_mem_operand.
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2000-01-27 Fred Fish <fnf@be.com>
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* gthr-posix.h: Fix typo; compatibily -> compatibility.
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@ -25,9 +25,10 @@ Boston, MA 02111-1307, USA.
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/* Compile for the floating point unit & 32532 by default;
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Don't assume SB is zero;
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Don't use bitfield instructions;
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FPU is 32381; */
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FPU is 32381;
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Use multiply-add instructions */
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#define TARGET_DEFAULT (1 + 24 + 32 + 64 + 256)
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#define TARGET_DEFAULT (1 + 24 + 32 + 64 + 256 + 512)
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/* 32-bit alignment for efficiency */
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@ -110,4 +111,3 @@ Boston, MA 02111-1307, USA.
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/* Until they use ELF or something that handles dwarf2 unwinds
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and initialization stuff better. */
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#define DWARF2_UNWIND_INFO 0
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@ -69,9 +69,9 @@ hard_regno_mode_ok (regno, mode)
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int regno;
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enum machine_mode mode;
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{
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int size = GET_MODE_UNIT_SIZE(mode);
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int size = GET_MODE_UNIT_SIZE (mode);
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if (FLOAT_MODE_P(mode))
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if (FLOAT_MODE_P (mode))
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{
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if (size == UNITS_PER_WORD && regno < L1_REGNUM)
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return 1;
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@ -90,20 +90,20 @@ hard_regno_mode_ok (regno, mode)
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return 0;
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}
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int register_move_cost(CLASS1, CLASS2)
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int register_move_cost (CLASS1, CLASS2)
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enum reg_class CLASS1;
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enum reg_class CLASS2;
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{
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if (CLASS1 == NO_REGS || CLASS2 == NO_REGS)
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return 2;
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if((SUBSET_P(CLASS1, FP_REGS) && !SUBSET_P(CLASS2, FP_REGS))
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|| (!SUBSET_P(CLASS1, FP_REGS) && SUBSET_P(CLASS2, FP_REGS)))
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if ((SUBSET_P (CLASS1, FP_REGS) && !SUBSET_P (CLASS2, FP_REGS))
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|| (!SUBSET_P (CLASS1, FP_REGS) && SUBSET_P (CLASS2, FP_REGS)))
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return 8;
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if (((CLASS1) == STACK_POINTER_REG && !SUBSET_P(CLASS2,GENERAL_REGS))
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|| ((CLASS2) == STACK_POINTER_REG && !SUBSET_P(CLASS1,GENERAL_REGS)))
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if (((CLASS1) == STACK_POINTER_REG && !SUBSET_P (CLASS2,GENERAL_REGS))
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|| ((CLASS2) == STACK_POINTER_REG && !SUBSET_P (CLASS1,GENERAL_REGS)))
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return 6;
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if (((CLASS1) == FRAME_POINTER_REG && !SUBSET_P(CLASS2,GENERAL_REGS))
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|| ((CLASS2) == FRAME_POINTER_REG && !SUBSET_P(CLASS1,GENERAL_REGS)))
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if (((CLASS1) == FRAME_POINTER_REG && !SUBSET_P (CLASS2,GENERAL_REGS))
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|| ((CLASS2) == FRAME_POINTER_REG && !SUBSET_P (CLASS1,GENERAL_REGS)))
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return 6;
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return 2;
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}
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@ -111,13 +111,13 @@ int register_move_cost(CLASS1, CLASS2)
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#if 0
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/* We made the insn definitions copy from floating point to general
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registers via the stack. */
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int secondary_memory_needed(CLASS1, CLASS2, M)
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int secondary_memory_needed (CLASS1, CLASS2, M)
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enum reg_class CLASS1;
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enum reg_class CLASS2;
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enum machine_mode M;
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{
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int ret = ((SUBSET_P(CLASS1, FP_REGS) && !SUBSET_P(CLASS2, FP_REGS))
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|| (!SUBSET_P(CLASS1, FP_REGS) && SUBSET_P(CLASS2, FP_REGS)));
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int ret = ((SUBSET_P (CLASS1, FP_REGS) && !SUBSET_P (CLASS2, FP_REGS))
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|| (!SUBSET_P (CLASS1, FP_REGS) && SUBSET_P (CLASS2, FP_REGS)));
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return ret;
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}
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#endif
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@ -133,28 +133,34 @@ calc_address_cost (operand)
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{
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int i;
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int cost = 0;
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if (GET_CODE (operand) == MEM)
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cost += 3;
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if (GET_CODE (operand) == MULT)
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cost += 2;
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#if 0
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if (GET_CODE (operand) == REG)
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cost += 1; /* not really, but the documentation
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says different amount of registers
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shouldn't return the same costs */
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#endif
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switch (GET_CODE (operand))
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{
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case REG:
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case CONST:
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case CONST_INT:
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case CONST_DOUBLE:
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case SYMBOL_REF:
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case LABEL_REF:
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cost += 1;
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break;
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case POST_DEC:
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case PRE_DEC:
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break;
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case CONST_INT:
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if (INTVAL (operand) <= 7 && INTVAL (operand) >= -8)
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break;
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if (INTVAL (operand) < 0x2000 && INTVAL (operand) >= -0x2000)
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{
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cost +=1;
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break;
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}
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case CONST:
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case LABEL_REF:
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case SYMBOL_REF:
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cost +=3;
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break;
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case CONST_DOUBLE:
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cost += 5;
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break;
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case MEM:
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cost += calc_address_cost (XEXP (operand, 0));
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break;
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@ -196,6 +202,7 @@ secondary_reload_class (class, mode, in)
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/* The expression to be build is BASE[INDEX:SCALE]. To recognize this,
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scale must be converted from an exponent (from ASHIFT) to a
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multiplier (for MULT). */
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static rtx
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gen_indexed_expr (base, index, scale)
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rtx base, index, scale;
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@ -212,20 +219,6 @@ gen_indexed_expr (base, index, scale)
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return addr;
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}
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/* Return 1 if OP is a valid operand of mode MODE. This
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predicate rejects operands which do not have a mode
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(such as CONST_INT which are VOIDmode). */
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int
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reg_or_mem_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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return (GET_MODE (op) == mode
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&& (GET_CODE (op) == REG
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|| GET_CODE (op) == SUBREG
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|| GET_CODE (op) == MEM));
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}
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/* Split one or more DImode RTL references into pairs of SImode
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references. The RTL can be REG, offsettable MEM, integer constant, or
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@ -256,7 +249,7 @@ split_di (operands, num, lo_half, hi_half)
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hi_half[num] = adj_offsettable_operand (operands[num], 4);
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}
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else
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abort();
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abort ();
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}
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}
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@ -414,7 +407,7 @@ output_move_double (operands)
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operands[3] is the alignment. */
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static void
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move_tail(operands, bytes, offset)
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move_tail (operands, bytes, offset)
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rtx operands[];
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int bytes;
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int offset;
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@ -422,21 +415,21 @@ move_tail(operands, bytes, offset)
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if (bytes & 2)
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{
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rtx src, dest;
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dest = change_address(operands[0], HImode,
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plus_constant(XEXP(operands[0], 0), offset));
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src = change_address(operands[1], HImode,
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plus_constant(XEXP(operands[1], 0), offset));
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emit_move_insn(dest, src);
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dest = change_address (operands[0], HImode,
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plus_constant (XEXP (operands[0], 0), offset));
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src = change_address (operands[1], HImode,
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plus_constant (XEXP (operands[1], 0), offset));
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emit_move_insn (dest, src);
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offset += 2;
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}
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if (bytes & 1)
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{
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rtx src, dest;
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dest = change_address(operands[0], QImode,
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plus_constant(XEXP(operands[0], 0), offset));
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src = change_address(operands[1], QImode,
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plus_constant(XEXP(operands[1], 0), offset));
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emit_move_insn(dest, src);
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dest = change_address (operands[0], QImode,
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plus_constant (XEXP (operands[0], 0), offset));
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src = change_address (operands[1], QImode,
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plus_constant (XEXP (operands[1], 0), offset));
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emit_move_insn (dest, src);
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}
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}
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@ -449,9 +442,9 @@ expand_block_move (operands)
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int constp = (GET_CODE (bytes_rtx) == CONST_INT);
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int bytes = (constp ? INTVAL (bytes_rtx) : 0);
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int align = INTVAL (align_rtx);
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rtx src_reg = gen_rtx(REG, Pmode, 1);
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rtx dest_reg = gen_rtx(REG, Pmode, 2);
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rtx count_reg = gen_rtx(REG, SImode, 0);
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rtx src_reg = gen_rtx_REG (Pmode, 1);
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rtx dest_reg = gen_rtx_REG (Pmode, 2);
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rtx count_reg = gen_rtx_REG (SImode, 0);
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if (constp && bytes <= 0)
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return;
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@ -460,34 +453,34 @@ expand_block_move (operands)
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{
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int words = bytes >> 2;
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if (words)
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{
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if (words < 3 || flag_unroll_loops)
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{
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int offset = 0;
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for (; words; words--, offset += 4)
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{
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rtx src, dest;
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dest = change_address(operands[0], SImode,
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plus_constant(XEXP(operands[0], 0), offset));
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src = change_address(operands[1], SImode,
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plus_constant(XEXP(operands[1], 0), offset));
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emit_move_insn(dest, src);
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}
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}
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else
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{
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/* Use movmd. It is slower than multiple movd's but more
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compact. It is also slower than movsd for large copies
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but causes less registers reloading so is better than movsd
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for small copies. */
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rtx src, dest;
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dest = copy_addr_to_reg (XEXP(operands[0], 0));
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src = copy_addr_to_reg (XEXP(operands[1], 0));
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{
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if (words < 3 || flag_unroll_loops)
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{
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int offset = 0;
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for (; words; words--, offset += 4)
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{
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rtx src, dest;
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dest = change_address (operands[0], SImode,
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plus_constant (XEXP (operands[0], 0), offset));
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src = change_address (operands[1], SImode,
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plus_constant (XEXP (operands[1], 0), offset));
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emit_move_insn (dest, src);
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}
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}
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else
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{
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/* Use movmd. It is slower than multiple movd's but more
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compact. It is also slower than movsd for large copies
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but causes less registers reloading so is better than movsd
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for small copies. */
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rtx src, dest;
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dest = copy_addr_to_reg (XEXP (operands[0], 0));
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src = copy_addr_to_reg (XEXP (operands[1], 0));
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emit_insn(gen_movstrsi2(dest, src, GEN_INT(words)));
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}
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}
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move_tail(operands, bytes & 3, bytes & ~3);
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emit_insn (gen_movstrsi2(dest, src, GEN_INT (words)));
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}
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}
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move_tail (operands, bytes & 3, bytes & ~3);
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return;
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}
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@ -495,11 +488,13 @@ expand_block_move (operands)
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align = UNITS_PER_WORD;
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/* Move the address into scratch registers. */
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emit_insn(gen_rtx(CLOBBER, VOIDmode, dest_reg));
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emit_move_insn(dest_reg, XEXP (operands[0], 0));
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emit_insn(gen_rtx(CLOBBER, VOIDmode, src_reg));
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emit_move_insn(src_reg, XEXP (operands[1], 0));
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emit_insn(gen_rtx(CLOBBER, VOIDmode, count_reg));
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emit_insn (gen_rtx_CLOBBER (VOIDmode, dest_reg));
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emit_move_insn (dest_reg, XEXP (operands[0], 0));
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operands[0] = gen_rtx_MEM (SImode, dest_reg);
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emit_insn (gen_rtx_CLOBBER (VOIDmode, src_reg));
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emit_move_insn (src_reg, XEXP (operands[1], 0));
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operands[1] = gen_rtx_MEM (SImode, src_reg);
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emit_insn (gen_rtx_CLOBBER (VOIDmode, count_reg));
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if (constp && (align == UNITS_PER_WORD || bytes < MAX_UNALIGNED_COPY))
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{
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@ -508,20 +503,27 @@ expand_block_move (operands)
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*/
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if (bytes >> 2)
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{
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emit_move_insn(count_reg, GEN_INT(bytes >> 2));
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emit_insn(gen_movstrsi1 (GEN_INT(4)));
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emit_move_insn (count_reg, GEN_INT (bytes >> 2));
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emit_insn (gen_movstrsi1 (GEN_INT (4)));
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}
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/* insns to copy rest */
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move_tail(operands, bytes & 3, bytes & ~3);
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move_tail (operands, bytes & 3, 0);
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}
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else if (align == UNITS_PER_WORD)
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{
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/* insns to copy by words */
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emit_insn(gen_lshrsi3 (count_reg, bytes_rtx, GEN_INT(2)));
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emit_insn(gen_movstrsi1 (GEN_INT(4)));
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/* insns to copy rest */
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emit_insn(gen_andsi3 (count_reg, bytes_rtx, GEN_INT(3)));
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emit_insn(gen_movstrsi1 (const1_rtx));
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emit_insn (gen_lshrsi3 (count_reg, bytes_rtx, GEN_INT (2)));
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emit_insn (gen_movstrsi1 (GEN_INT (4)));
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if (constp)
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{
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move_tail (operands, bytes & 3, 0);
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}
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else
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{
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/* insns to copy rest */
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emit_insn (gen_andsi3 (count_reg, bytes_rtx, GEN_INT (3)));
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emit_insn (gen_movstrsi1 (const1_rtx));
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}
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}
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else
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{
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@ -531,32 +533,32 @@ expand_block_move (operands)
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rtx aligned_label = gen_label_rtx ();
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rtx bytes_reg;
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bytes_reg = copy_to_mode_reg(SImode, bytes_rtx);
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bytes_reg = copy_to_mode_reg (SImode, bytes_rtx);
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if (!constp)
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{
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/* Emit insns to test and skip over the alignment if it is
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* not worth it. This doubles as a test to ensure that the alignment
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* operation can't copy too many bytes
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*/
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emit_insn(gen_cmpsi (bytes_reg, GEN_INT(MAX_UNALIGNED_COPY)));
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emit_insn (gen_cmpsi (bytes_reg, GEN_INT (MAX_UNALIGNED_COPY)));
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emit_jump_insn (gen_blt (aligned_label));
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}
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/* Emit insns to do alignment at run time */
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emit_insn(gen_negsi2 (count_reg, src_reg));
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emit_insn(gen_andsi3 (count_reg, count_reg, GEN_INT(3)));
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emit_insn(gen_subsi3 (bytes_reg, bytes_reg, count_reg));
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emit_insn(gen_movstrsi1 (const1_rtx));
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emit_insn (gen_negsi2 (count_reg, src_reg));
|
||||
emit_insn (gen_andsi3 (count_reg, count_reg, GEN_INT (3)));
|
||||
emit_insn (gen_subsi3 (bytes_reg, bytes_reg, count_reg));
|
||||
emit_insn (gen_movstrsi1 (const1_rtx));
|
||||
if (!constp)
|
||||
emit_label (aligned_label);
|
||||
|
||||
/* insns to copy by words */
|
||||
emit_insn (gen_lshrsi3 (count_reg, bytes_reg, GEN_INT(2)));
|
||||
emit_insn(gen_movstrsi1 (GEN_INT(4)));
|
||||
emit_insn (gen_lshrsi3 (count_reg, bytes_reg, GEN_INT (2)));
|
||||
emit_insn (gen_movstrsi1 (GEN_INT (4)));
|
||||
|
||||
/* insns to copy rest */
|
||||
emit_insn (gen_andsi3 (count_reg, bytes_reg, GEN_INT(3)));
|
||||
emit_insn(gen_movstrsi1 (const1_rtx));
|
||||
emit_insn (gen_andsi3 (count_reg, bytes_reg, GEN_INT (3)));
|
||||
emit_insn (gen_movstrsi1 (const1_rtx));
|
||||
}
|
||||
}
|
||||
|
||||
@ -759,7 +761,7 @@ print_operand (file, x, code)
|
||||
{
|
||||
union { double d; int i[2]; } u;
|
||||
u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
|
||||
PUT_IMMEDIATE_PREFIX(file);
|
||||
PUT_IMMEDIATE_PREFIX (file);
|
||||
#ifdef SEQUENT_ASM
|
||||
/* Sequent likes its floating point constants as integers */
|
||||
fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
|
||||
@ -798,10 +800,10 @@ print_operand (file, x, code)
|
||||
&& GET_CODE (x) == CONST
|
||||
&& symbolic_reference_mentioned_p (x))
|
||||
{
|
||||
fprintf(stderr, "illegal constant for pic-mode: \n");
|
||||
print_rtl(stderr, x);
|
||||
fprintf(stderr, "\nGET_CODE (x) == %d, CONST == %d, symbolic_reference_mentioned_p (x) == %d\n",
|
||||
GET_CODE (x), CONST, symbolic_reference_mentioned_p(x));
|
||||
fprintf (stderr, "illegal constant for pic-mode: \n");
|
||||
print_rtl (stderr, x);
|
||||
fprintf (stderr, "\nGET_CODE (x) == %d, CONST == %d, symbolic_reference_mentioned_p (x) == %d\n",
|
||||
GET_CODE (x), CONST, symbolic_reference_mentioned_p (x));
|
||||
abort ();
|
||||
}
|
||||
else if (flag_pic
|
||||
@ -1025,7 +1027,7 @@ print_operand_address (file, addr)
|
||||
fprintf (file, "(sb))");
|
||||
break;
|
||||
case MEM:
|
||||
addr = XEXP(base,0);
|
||||
addr = XEXP (base,0);
|
||||
base = NULL;
|
||||
offset = NULL;
|
||||
while (addr != NULL)
|
||||
@ -1127,46 +1129,46 @@ output_shift_insn (operands)
|
||||
if (GET_CODE (operands[2]) == CONST_INT
|
||||
&& INTVAL (operands[2]) > 0
|
||||
&& INTVAL (operands[2]) <= 3)
|
||||
{
|
||||
if (GET_CODE (operands[0]) == REG)
|
||||
{
|
||||
if (GET_CODE (operands[1]) == REG)
|
||||
{
|
||||
if (REGNO (operands[0]) == REGNO (operands[1]))
|
||||
{
|
||||
if (operands[2] == const1_rtx)
|
||||
return "addd %0,%0";
|
||||
else if (INTVAL (operands[2]) == 2)
|
||||
return "addd %0,%0\n\taddd %0,%0";
|
||||
}
|
||||
if (operands[2] == const1_rtx)
|
||||
return "movd %1,%0\n\taddd %0,%0";
|
||||
{
|
||||
if (GET_CODE (operands[0]) == REG)
|
||||
{
|
||||
if (GET_CODE (operands[1]) == REG)
|
||||
{
|
||||
if (REGNO (operands[0]) == REGNO (operands[1]))
|
||||
{
|
||||
if (operands[2] == const1_rtx)
|
||||
return "addd %0,%0";
|
||||
else if (INTVAL (operands[2]) == 2)
|
||||
return "addd %0,%0\n\taddd %0,%0";
|
||||
}
|
||||
if (operands[2] == const1_rtx)
|
||||
return "movd %1,%0\n\taddd %0,%0";
|
||||
|
||||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||||
return "addr %a1,%0";
|
||||
}
|
||||
if (operands[2] == const1_rtx)
|
||||
return "movd %1,%0\n\taddd %0,%0";
|
||||
}
|
||||
else if (GET_CODE (operands[1]) == REG)
|
||||
{
|
||||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||||
return "addr %a1,%0";
|
||||
}
|
||||
else if (INTVAL (operands[2]) == 1
|
||||
&& GET_CODE (operands[1]) == MEM
|
||||
&& rtx_equal_p (operands [0], operands[1]))
|
||||
{
|
||||
rtx temp = XEXP (operands[1], 0);
|
||||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||||
return "addr %a1,%0";
|
||||
}
|
||||
if (operands[2] == const1_rtx)
|
||||
return "movd %1,%0\n\taddd %0,%0";
|
||||
}
|
||||
else if (GET_CODE (operands[1]) == REG)
|
||||
{
|
||||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||||
return "addr %a1,%0";
|
||||
}
|
||||
else if (INTVAL (operands[2]) == 1
|
||||
&& GET_CODE (operands[1]) == MEM
|
||||
&& rtx_equal_p (operands [0], operands[1]))
|
||||
{
|
||||
rtx temp = XEXP (operands[1], 0);
|
||||
|
||||
if (GET_CODE (temp) == REG
|
||||
|| (GET_CODE (temp) == PLUS
|
||||
&& GET_CODE (XEXP (temp, 0)) == REG
|
||||
&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
|
||||
return "addd %0,%0";
|
||||
}
|
||||
else return "ashd %2,%0";
|
||||
}
|
||||
if (GET_CODE (temp) == REG
|
||||
|| (GET_CODE (temp) == PLUS
|
||||
&& GET_CODE (XEXP (temp, 0)) == REG
|
||||
&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
|
||||
return "addd %0,%0";
|
||||
}
|
||||
else return "ashd %2,%0";
|
||||
}
|
||||
return "ashd %2,%0";
|
||||
}
|
||||
|
||||
|
||||
@ -66,13 +66,8 @@ extern int target_flags;
|
||||
#define TARGET_32081 (target_flags & 1)
|
||||
#define TARGET_32381 (target_flags & 256)
|
||||
|
||||
/* The use of multiply-add instructions is optional because it can
|
||||
* cause an abort due to being unable to find a spill register. The
|
||||
* main problem is that the multiply-add instructions require f0 and
|
||||
* f0 is not available for spilling because it is "explicitly
|
||||
* mentioned" in the rtl for function return values. This can be fixed
|
||||
* by defining SMALL_REGISTER_CLASSES, but that causes worse code for
|
||||
* the (more common) integer case. We really need better reload code.
|
||||
/* The use of multiply-add instructions is optional because there may
|
||||
* be cases where it produces worse code.
|
||||
*/
|
||||
|
||||
#define TARGET_MULT_ADD (target_flags & 512)
|
||||
@ -103,27 +98,29 @@ extern int target_flags;
|
||||
where VALUE is the bits to set or minus the bits to clear.
|
||||
An empty string NAME is used to identify the default VALUE. */
|
||||
|
||||
#define TARGET_SWITCHES \
|
||||
{ { "32081", 1}, \
|
||||
{ "soft-float", -257}, \
|
||||
{ "rtd", 2}, \
|
||||
{ "nortd", -2}, \
|
||||
{ "regparm", 4}, \
|
||||
{ "noregparm", -4}, \
|
||||
{ "32532", 24}, \
|
||||
{ "32332", -8}, \
|
||||
{ "32332", 16}, \
|
||||
{ "32032", -24}, \
|
||||
{ "sb", -32}, \
|
||||
{ "nosb", 32}, \
|
||||
{ "bitfield", -64}, \
|
||||
{ "nobitfield", 64}, \
|
||||
{ "himem", 128}, \
|
||||
{ "nohimem", -128}, \
|
||||
{ "32381", 256}, \
|
||||
{ "mult-add", 512}, \
|
||||
{ "nomult-add", -512}, \
|
||||
{ "", TARGET_DEFAULT}}
|
||||
#define TARGET_SWITCHES \
|
||||
{ { "32081", 1, "Use hardware fp"}, \
|
||||
{ "soft-float", -257, "Don't use hardware fp"}, \
|
||||
{ "rtd", 2, "Alternative calling convention"}, \
|
||||
{ "nortd", -2, "Use normal calling convention"}, \
|
||||
{ "regparm", 4, "Pass some arguments in registers"}, \
|
||||
{ "noregparm", -4, "Pass all arguments on stack"}, \
|
||||
{ "32532", 24, "Optimize for 32532 cpu"}, \
|
||||
{ "32332", 16, "Optimize for 32332 cpu"}, \
|
||||
{ "32332", -8, 0}, \
|
||||
{ "32032", -24, "Optimize for 32032"}, \
|
||||
{ "sb", -32, "Register sb is zero. Use for absolute addressing"}, \
|
||||
{ "nosb", 32, "Do not use register sb"}, \
|
||||
{ "bitfield", -64, "Do not use bitfield instructions"}, \
|
||||
{ "nobitfield", 64, "Use bitfield instructions"}, \
|
||||
{ "himem", 128, "Generate code for high memory"}, \
|
||||
{ "nohimem", -128, "Generate code for low memory"}, \
|
||||
{ "32381", 256, "32381 fpu"}, \
|
||||
{ "mult-add", 512, "Use multiply-accumulate fp instructions"}, \
|
||||
{ "nomult-add", -512, "Do not use multiply-accumulate fp instructions" }, \
|
||||
{ "src", 1024, "\"Small register classes\" kludge"}, \
|
||||
{ "nosrc", -1024, "No \"Small register classes\" kludge"}, \
|
||||
{ "", TARGET_DEFAULT, 0}}
|
||||
|
||||
/* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */
|
||||
|
||||
@ -304,6 +301,11 @@ while (0)
|
||||
: (REGNO) == FRAME_POINTER_REGNUM? 17 \
|
||||
: 16)
|
||||
|
||||
/* dwarf2out.c can't understand the funny DBX register numbering.
|
||||
* We use dwarf2out.c for exception handling even though we use DBX
|
||||
* for debugging
|
||||
*/
|
||||
#define DWARF_FRAME_REGNUM(REGNO) (REGNO)
|
||||
|
||||
|
||||
|
||||
@ -408,13 +410,23 @@ enum reg_class
|
||||
This is an initializer for a vector of HARD_REG_SET
|
||||
of length N_REG_CLASSES. */
|
||||
|
||||
#define REG_CLASS_CONTENTS {{0}, {0x00ff}, {0x100}, {0x300}, {0xff00}, \
|
||||
{0xffff00}, {0xffffff}, {0x1000000}, {0x2000000}, \
|
||||
{0x30000ff}, {0x3ffffff} }
|
||||
#define REG_CLASS_CONTENTS \
|
||||
{{0}, /* NO_REGS */ \
|
||||
{0x00ff}, /* GENERAL_REGS */ \
|
||||
{0x100}, /* FLOAT_REG0 */ \
|
||||
{0x300}, /* LONG_FLOAT_REG0 */ \
|
||||
{0xff00}, /* FLOAT_REGS */ \
|
||||
{0xffff00}, /* FP_REGS */ \
|
||||
{0xffffff}, /* GEN_AND_FP_REGS */ \
|
||||
{0x1000000}, /* FRAME_POINTER_REG */ \
|
||||
{0x2000000}, /* STACK_POINTER_REG */ \
|
||||
{0x30000ff}, /* GEN_AND_MEM_REGS */ \
|
||||
{0x3ffffff} /* ALL_REGS */ \
|
||||
}
|
||||
|
||||
#define SUBSET_P(CLASS1, CLASS2) \
|
||||
((ns32k_reg_class_contents[CLASS1][0] & ~ns32k_reg_class_contents[CLASS2][0]) \
|
||||
== 0)
|
||||
#define SUBSET_P(CLASS1, CLASS2) \
|
||||
((ns32k_reg_class_contents[CLASS1][0] \
|
||||
& ~ns32k_reg_class_contents[CLASS2][0]) == 0)
|
||||
|
||||
/* The same information, inverted:
|
||||
Return the class number of the smallest class containing
|
||||
@ -1036,10 +1048,10 @@ __transfer_from_trampoline () \
|
||||
secondary_memory_needed(CLASS1, CLASS2, M)
|
||||
#endif
|
||||
|
||||
/* SMALL_REGISTER_CLASSES is true only if we have said we are using the
|
||||
* multiply-add instructions.
|
||||
*/
|
||||
#define SMALL_REGISTER_CLASSES (target_flags & 512)
|
||||
/* SMALL_REGISTER_CLASSES is a run time option. This should no longer
|
||||
be necessay and should go when we have confidence that we won't run
|
||||
out of spill registers */
|
||||
#define SMALL_REGISTER_CLASSES (target_flags & 1024)
|
||||
|
||||
/* A C expression whose value is nonzero if pseudos that have been
|
||||
assigned to registers of class CLASS would likely be spilled
|
||||
@ -1144,13 +1156,14 @@ __transfer_from_trampoline () \
|
||||
|
||||
/* Go to ADDR if X is a valid address not using indexing.
|
||||
(This much is the easy part.) */
|
||||
#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
|
||||
{ if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \
|
||||
if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \
|
||||
if (GET_CODE (X) == PLUS) \
|
||||
if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))) \
|
||||
if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0))) \
|
||||
goto ADDR; \
|
||||
#define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
|
||||
{ \
|
||||
if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \
|
||||
if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \
|
||||
if (GET_CODE (X) == PLUS) \
|
||||
if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))) \
|
||||
if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0))) \
|
||||
goto ADDR; \
|
||||
}
|
||||
|
||||
/* Go to ADDR if X is a valid address not using indexing.
|
||||
@ -1189,11 +1202,11 @@ __transfer_from_trampoline () \
|
||||
((xfoo2 < 4 && xfoo2 != 2) || xfoo2 == 7))
|
||||
|
||||
/* Note that xfoo0, xfoo1, xfoo2 are used in some of the submacros above. */
|
||||
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
||||
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
|
||||
{ register rtx xfooy, xfoo0, xfoo1; \
|
||||
unsigned xfoo2; \
|
||||
xfooy = X; \
|
||||
if (flag_pic && ! current_function_uses_pic_offset_table \
|
||||
if (flag_pic && cfun && ! current_function_uses_pic_offset_table \
|
||||
&& global_symbolic_reference_mentioned_p (X, 1)) \
|
||||
current_function_uses_pic_offset_table = 1; \
|
||||
GO_IF_NONINDEXED_ADDRESS (xfooy, ADDR); \
|
||||
@ -1212,8 +1225,8 @@ __transfer_from_trampoline () \
|
||||
else if (GET_CODE (xfooy) == PRE_DEC) \
|
||||
{ \
|
||||
if (REGNO (XEXP (xfooy, 0)) == STACK_POINTER_REGNUM) goto ADDR; \
|
||||
else abort (); \
|
||||
} \
|
||||
else abort (); \
|
||||
}
|
||||
|
||||
/* Try machine-dependent ways of modifying an illegitimate address
|
||||
@ -1679,7 +1692,7 @@ do { \
|
||||
|
||||
extern unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1];
|
||||
extern const char *const ns32k_out_reg_names[];
|
||||
extern enum reg_class regclass_map[]; /* smalled class containing REGNO */
|
||||
extern enum reg_class regclass_map[]; /* smallest class containing REGNO */
|
||||
|
||||
/*
|
||||
Local variables:
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,7 @@
|
||||
/* Config file for ns32k running system V. */
|
||||
|
||||
#include "ns32k/xm-ns32k.h"
|
||||
#define memcpy(src,dst,len) bcopy ((dst),(src),(len))
|
||||
#define memset gcc_memset
|
||||
#define memcmp(left,right,len) bcmp ((left),(right),(len))
|
||||
|
||||
#define USG
|
||||
|
||||
@ -1,8 +1,3 @@
|
||||
/* Configuration for GCC for ns32k running NetBSD as host. */
|
||||
|
||||
#include <ns32k/xm-ns32k.h>
|
||||
|
||||
/* ns32k/xm-ns32k.h defines these macros, but we don't need them */
|
||||
#undef memcmp
|
||||
#undef memcpy
|
||||
#undef memset
|
||||
/* Nothing needs to be done */
|
||||
|
||||
@ -36,7 +36,3 @@ Boston, MA 02111-1307, USA. */
|
||||
/* Arguments to use with `exit'. */
|
||||
#define SUCCESS_EXIT_CODE 0
|
||||
#define FATAL_EXIT_CODE 33
|
||||
|
||||
#define memcpy(src,dst,len) bcopy ((dst),(src),(len))
|
||||
#define memset gcc_memset
|
||||
#define memcmp(left,right,len) bcmp ((left),(right),(len))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user