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mips.md (length): Don't use mips_fetch_insns for indexed loads and stores.

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* config/mips/mips.md (length): Don't use mips_fetch_insns for indexed
	loads and stores.
	(*lwxc1_<mode>, *ldxc1_<mode>, *swxc1_<mode>, *sdxc1_<mode>): Name
	formerly unnamed patterns.  Redefine using :P for the address.  Remove
	explicit length attributes.

From-SVN: r86419
This commit is contained in:
Richard Sandiford 2004-08-23 08:20:53 +00:00 committed by Richard Sandiford
parent a3631d9785
commit 4d06ed0a96
2 changed files with 30 additions and 66 deletions
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8
gcc/ChangeLog
View File

@ -1,3 +1,11 @@
2004-08-23 Richard Sandiford <rsandifo@redhat.com>
* config/mips/mips.md (length): Don't use mips_fetch_insns for indexed
loads and stores.
(*lwxc1_<mode>, *ldxc1_<mode>, *swxc1_<mode>, *sdxc1_<mode>): Name
formerly unnamed patterns. Redefine using :P for the address. Remove
explicit length attributes.
2004-08-23 Zdenek Dvorak <rakdver@atrey.karlin.mff.cuni.cz>
* tree-ssa-loop-im.c (fem_single_reachable_address, for_each_memref):

88
gcc/config/mips/mips.md
View File

@ -181,9 +181,9 @@
(eq_attr "type" "const")
(symbol_ref "mips_const_insns (operands[1]) * 4")
(eq_attr "type" "load,fpload,fpidxload")
(eq_attr "type" "load,fpload")
(symbol_ref "mips_fetch_insns (operands[1]) * 4")
(eq_attr "type" "store,fpstore,fpidxstore")
(eq_attr "type" "store,fpstore")
(symbol_ref "mips_fetch_insns (operands[0]) * 4")
;; In the worst case, a call macro will take 8 instructions:
@ -3717,85 +3717,41 @@ beq\t%2,%.,1b\;\
;; these instructions can only be used to load and store floating
;; point registers, that would probably cause trouble in reload.
(define_insn ""
(define_insn "*lwxc1_<mode>"
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
(mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
[(set_attr "type" "fpidxload")
(set_attr "mode" "SF")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f")
(mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"lwxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
(set_attr "mode" "SF")
(set_attr "length" "4")])
(define_insn ""
(define_insn "*ldxc1_<mode>"
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d"))))]
(mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
(set_attr "mode" "DF")
(set_attr "length" "4")])
[(set_attr "type" "fpidxload")
(set_attr "mode" "DF")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f")
(mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d"))))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"ldxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxload")
(set_attr "mode" "DF")
(set_attr "length" "4")])
(define_insn ""
[(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(define_insn "*swxc1_<mode>"
[(set (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
(set_attr "mode" "SF")
(set_attr "length" "4")])
[(set_attr "type" "fpidxstore")
(set_attr "mode" "SF")])
(define_insn ""
[(set (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))
(match_operand:SF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT"
"swxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
(set_attr "mode" "SF")
(set_attr "length" "4")])
(define_insn ""
[(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(define_insn "*sdxc1_<mode>"
[(set (mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
(match_operand:P 2 "register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
(set_attr "mode" "DF")
(set_attr "length" "4")])
(define_insn ""
[(set (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))
(match_operand:DF 0 "register_operand" "f"))]
"ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"sdxc1\t%0,%1(%2)"
[(set_attr "type" "fpidxstore")
(set_attr "mode" "DF")
(set_attr "length" "4")])
[(set_attr "type" "fpidxstore")
(set_attr "mode" "DF")])
;; 16-bit Integer moves