AMD bdver2 Enablement
2011-07-12 Harsha Jagasia <harsha.jagasia@amd.com>
AMD bdver2 Enablement
* config.gcc (i[34567]86-*-linux* | ...): Add bdver2.
(case ${target}): Add bdver2.
* config/i386/driver-i386.c (host_detect_local_cpu): Let
-march=native recognize bdver2 processors.
* config/i386/i386-c.c (ix86_target_macros_internal): Add
bdver2 def_and_undef
* config/i386/i386.c (struct processor_costs bdver2_cost): New
bdver2 cost table.
(m_BDVER2): New definition.
(m_AMD_MULTIPLE): Includes m_BDVER2.
(initial_ix86_tune_features): Add bdver2 tuning.
(processor_target_table): Add bdver2 entry.
(static const char *const cpu_names): Add bdver2 entry.
(ix86_option_override_internal): Add bdver2 instruction sets.
(ix86_issue_rate): Add bdver2.
(ix86_adjust_cost): Add bdver2.
(has_dispatch): Add bdver2.
* config/i386/i386.h (TARGET_BDVER2): New definition.
(enum target_cpu_default): Add TARGET_CPU_DEFAULT_bdver2.
(enum processor_type): Add PROCESSOR_BDVER2.
* config/i386/i386.md (define_attr "cpu"): Add bdver2.
* config/i386/i386.opt ( mdispatch-scheduler): Add bdver2 to
description.
From-SVN: r176209
This commit is contained in:
Harsha Jagasia
Harsha Jagasia
parent
5756d08c25
commit
4d652a1865
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@ -1,3 +1,30 @@
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2011-07-12 Harsha Jagasia <harsha.jagasia@amd.com>
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AMD bdver2 Enablement
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* config.gcc (i[34567]86-*-linux* | ...): Add bdver2.
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(case ${target}): Add bdver2.
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* config/i386/driver-i386.c (host_detect_local_cpu): Let
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-march=native recognize bdver2 processors.
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* config/i386/i386-c.c (ix86_target_macros_internal): Add
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bdver2 def_and_undef
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* config/i386/i386.c (struct processor_costs bdver2_cost): New
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bdver2 cost table.
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(m_BDVER2): New definition.
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(m_AMD_MULTIPLE): Includes m_BDVER2.
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(initial_ix86_tune_features): Add bdver2 tuning.
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(processor_target_table): Add bdver2 entry.
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(static const char *const cpu_names): Add bdver2 entry.
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(ix86_option_override_internal): Add bdver2 instruction sets.
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(ix86_issue_rate): Add bdver2.
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(ix86_adjust_cost): Add bdver2.
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(has_dispatch): Add bdver2.
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* config/i386/i386.h (TARGET_BDVER2): New definition.
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(enum target_cpu_default): Add TARGET_CPU_DEFAULT_bdver2.
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(enum processor_type): Add PROCESSOR_BDVER2.
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* config/i386/i386.md (define_attr "cpu"): Add bdver2.
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* config/i386/i386.opt ( mdispatch-scheduler): Add bdver2 to
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description.
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2011-07-12 Richard Henderson <rth@redhat.com>
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PR target/49714
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@ -1289,7 +1289,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
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need_64bit_hwint=yes
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need_64bit_isa=yes
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case X"${with_cpu}" in
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Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
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Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
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;;
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X)
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if test x$with_cpu_64 = x; then
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@ -1298,7 +1298,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i
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;;
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*)
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echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
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echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
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echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
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exit 1
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;;
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esac
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@ -1414,7 +1414,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)
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need_64bit_hwint=yes
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need_64bit_isa=yes
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case X"${with_cpu}" in
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Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
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Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
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;;
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X)
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if test x$with_cpu_64 = x; then
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@ -1423,7 +1423,7 @@ i[34567]86-*-solaris2* | x86_64-*-solaris2.1[0-9]*)
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;;
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*)
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echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
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echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
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echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
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exit 1
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;;
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esac
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@ -1493,7 +1493,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
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if test x$enable_targets = xall; then
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tm_defines="${tm_defines} TARGET_BI_ARCH=1"
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case X"${with_cpu}" in
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Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
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Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3)
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;;
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X)
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if test x$with_cpu_64 = x; then
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@ -1502,7 +1502,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*)
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;;
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*)
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echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
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echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
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echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver2 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2
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exit 1
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;;
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esac
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@ -2748,6 +2748,10 @@ case ${target} in
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;;
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i686-*-* | i786-*-*)
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case ${target_noncanonical} in
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bdver2-*)
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arch=bdver2
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cpu=bdver2
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;;
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bdver1-*)
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arch=bdver1
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cpu=bdver1
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@ -2841,6 +2845,10 @@ case ${target} in
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;;
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x86_64-*-*)
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case ${target_noncanonical} in
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bdver2-*)
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arch=bdver2
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cpu=bdver2
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;;
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bdver1-*)
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arch=bdver1
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cpu=bdver1
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@ -3276,8 +3284,9 @@ case "${target}" in
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;;
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"" | x86-64 | generic | native \
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| k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \
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| opteron-sse3 | athlon-fx | bdver1 | btver1 | amdfam10 \
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| barcelona | nocona | core2 | corei7 | corei7-avx | atom)
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| opteron-sse3 | athlon-fx | bdver2 | bdver1 | btver1 \
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| amdfam10 | barcelona | nocona | core2 | corei7 \
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| corei7-avx | atom)
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# OK
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;;
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*)
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@ -499,6 +499,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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if (name == SIG_GEODE)
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processor = PROCESSOR_GEODE;
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else if (has_bmi)
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processor = PROCESSOR_BDVER2;
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else if (has_xop)
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processor = PROCESSOR_BDVER1;
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else if (has_sse4a && has_ssse3)
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@ -664,6 +666,9 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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case PROCESSOR_BDVER1:
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cpu = "bdver1";
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break;
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case PROCESSOR_BDVER2:
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cpu = "bdver2";
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break;
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case PROCESSOR_BTVER1:
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cpu = "btver1";
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break;
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@ -110,6 +110,10 @@ ix86_target_macros_internal (int isa_flag,
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def_or_undef (parse_in, "__bdver1");
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def_or_undef (parse_in, "__bdver1__");
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break;
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case PROCESSOR_BDVER2:
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def_or_undef (parse_in, "__bdver2");
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def_or_undef (parse_in, "__bdver2__");
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break;
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case PROCESSOR_BTVER1:
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def_or_undef (parse_in, "__btver1");
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def_or_undef (parse_in, "__btver1__");
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@ -198,6 +202,9 @@ ix86_target_macros_internal (int isa_flag,
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case PROCESSOR_BDVER1:
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def_or_undef (parse_in, "__tune_bdver1__");
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break;
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case PROCESSOR_BDVER2:
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def_or_undef (parse_in, "__tune_bdver2__");
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break;
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case PROCESSOR_BTVER1:
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def_or_undef (parse_in, "__tune_btver1__");
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break;
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@ -1338,6 +1338,93 @@ struct processor_costs bdver1_cost = {
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1, /* cond_not_taken_branch_cost. */
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};
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struct processor_costs bdver2_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (1), /* cost of a lea instruction */
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COSTS_N_INSNS (1), /* variable shift costs */
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COSTS_N_INSNS (1), /* constant shift costs */
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{COSTS_N_INSNS (4), /* cost of starting multiply for QI */
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COSTS_N_INSNS (4), /* HI */
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COSTS_N_INSNS (4), /* SI */
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COSTS_N_INSNS (6), /* DI */
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COSTS_N_INSNS (6)}, /* other */
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0, /* cost of multiply per each bit set */
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{COSTS_N_INSNS (19), /* cost of a divide/mod for QI */
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COSTS_N_INSNS (35), /* HI */
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COSTS_N_INSNS (51), /* SI */
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COSTS_N_INSNS (83), /* DI */
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COSTS_N_INSNS (83)}, /* other */
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COSTS_N_INSNS (1), /* cost of movsx */
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COSTS_N_INSNS (1), /* cost of movzx */
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8, /* "large" insn */
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9, /* MOVE_RATIO */
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4, /* cost for loading QImode using movzbl */
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{5, 5, 4}, /* cost of loading integer registers
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in QImode, HImode and SImode.
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Relative to reg-reg move (2). */
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{4, 4, 4}, /* cost of storing integer registers */
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2, /* cost of reg,reg fld/fst */
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{5, 5, 12}, /* cost of loading fp registers
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in SFmode, DFmode and XFmode */
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{4, 4, 8}, /* cost of storing fp registers
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in SFmode, DFmode and XFmode */
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2, /* cost of moving MMX register */
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{4, 4}, /* cost of loading MMX registers
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in SImode and DImode */
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{4, 4}, /* cost of storing MMX registers
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in SImode and DImode */
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2, /* cost of moving SSE register */
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{4, 4, 4}, /* cost of loading SSE registers
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in SImode, DImode and TImode */
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{4, 4, 4}, /* cost of storing SSE registers
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in SImode, DImode and TImode */
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2, /* MMX or SSE register to integer */
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/* On K8:
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MOVD reg64, xmmreg Double FSTORE 4
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MOVD reg32, xmmreg Double FSTORE 4
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On AMDFAM10:
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MOVD reg64, xmmreg Double FADD 3
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1/1 1/1
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MOVD reg32, xmmreg Double FADD 3
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1/1 1/1 */
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16, /* size of l1 cache. */
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2048, /* size of l2 cache. */
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64, /* size of prefetch block */
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/* New AMD processors never drop prefetches; if they cannot be performed
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immediately, they are queued. We set number of simultaneous prefetches
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to a large constant to reflect this (it probably is not a good idea not
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to limit number of prefetches at all, as their execution also takes some
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time). */
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100, /* number of parallel prefetches */
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2, /* Branch cost */
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COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */
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COSTS_N_INSNS (6), /* cost of FMUL instruction. */
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COSTS_N_INSNS (42), /* cost of FDIV instruction. */
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COSTS_N_INSNS (2), /* cost of FABS instruction. */
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COSTS_N_INSNS (2), /* cost of FCHS instruction. */
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COSTS_N_INSNS (52), /* cost of FSQRT instruction. */
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/* BDVER2 has optimized REP instruction for medium sized blocks, but for
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very small blocks it is better to use loop. For large blocks, libcall
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can do nontemporary accesses and beat inline considerably. */
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{{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}},
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{libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
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{{libcall, {{8, loop}, {24, unrolled_loop},
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{2048, rep_prefix_4_byte}, {-1, libcall}}},
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{libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}},
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6, /* scalar_stmt_cost. */
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4, /* scalar load_cost. */
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4, /* scalar_store_cost. */
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6, /* vec_stmt_cost. */
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0, /* vec_to_scalar_cost. */
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2, /* scalar_to_vec_cost. */
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4, /* vec_align_load_cost. */
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4, /* vec_unalign_load_cost. */
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4, /* vec_store_cost. */
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2, /* cond_taken_branch_cost. */
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1, /* cond_not_taken_branch_cost. */
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};
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struct processor_costs btver1_cost = {
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COSTS_N_INSNS (1), /* cost of an add instruction */
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COSTS_N_INSNS (2), /* cost of a lea instruction */
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@ -1813,8 +1900,10 @@ const struct processor_costs *ix86_cost = &pentium_cost;
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#define m_ATHLON_K8 (m_K8 | m_ATHLON)
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#define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
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#define m_BDVER1 (1<<PROCESSOR_BDVER1)
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#define m_BDVER2 (1<<PROCESSOR_BDVER2)
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#define m_BTVER1 (1<<PROCESSOR_BTVER1)
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#define m_AMD_MULTIPLE (m_K8 | m_ATHLON | m_AMDFAM10 | m_BDVER1 | m_BTVER1)
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#define m_BDVER (m_BDVER1 | m_BDVER2)
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#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1)
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#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
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#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
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@ -1856,7 +1945,7 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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~m_386,
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/* X86_TUNE_USE_SAHF */
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m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER1 | m_BTVER1
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m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER1
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| m_PENT4 | m_NOCONA | m_CORE2I7 | m_GENERIC,
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/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
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@ -1959,17 +2048,17 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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shows that disabling this option on P4 brings over 20% SPECfp regression,
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while enabling it on K8 brings roughly 2.4% regression that can be partly
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masked by careful scheduling of moves. */
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m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2I7 | m_GENERIC
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| m_AMDFAM10 | m_BDVER1,
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m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2I7 | m_GENERIC | m_AMDFAM10
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| m_BDVER,
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/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
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m_AMDFAM10 | m_BDVER1 | m_BTVER1 | m_COREI7,
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m_AMDFAM10 | m_BDVER | m_BTVER1 | m_COREI7,
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/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
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m_BDVER1 | m_COREI7,
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m_BDVER | m_COREI7,
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/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
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m_BDVER1,
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m_BDVER ,
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/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
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are resolved on SSE register parts instead of whole registers, so we may
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@ -2002,7 +2091,7 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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~(m_AMD_MULTIPLE | m_GENERIC),
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/* X86_TUNE_INTER_UNIT_CONVERSIONS */
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~(m_AMDFAM10 | m_BDVER1),
|
||||
~(m_AMDFAM10 | m_BDVER ),
|
||||
|
||||
/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
|
||||
than 4 branch instructions in the 16 byte window. */
|
||||
|
|
@ -2041,11 +2130,11 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
|
|||
|
||||
/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
|
||||
vector path on AMD machines. */
|
||||
m_K8 | m_CORE2I7_64 | m_GENERIC64 | m_AMDFAM10 | m_BDVER1 | m_BTVER1,
|
||||
m_K8 | m_CORE2I7_64 | m_GENERIC64 | m_AMDFAM10 | m_BDVER | m_BTVER1,
|
||||
|
||||
/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
|
||||
machines. */
|
||||
m_K8 | m_CORE2I7_64 | m_GENERIC64 | m_AMDFAM10 | m_BDVER1 | m_BTVER1,
|
||||
m_K8 | m_CORE2I7_64 | m_GENERIC64 | m_AMDFAM10 | m_BDVER | m_BTVER1,
|
||||
|
||||
/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
|
||||
than a MOV. */
|
||||
|
|
@ -2071,7 +2160,7 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
|
|||
/* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
|
||||
with a subsequent conditional jump instruction into a single
|
||||
compare-and-branch uop. */
|
||||
m_BDVER1,
|
||||
m_BDVER ,
|
||||
|
||||
/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
|
||||
will impact LEA instruction selection. */
|
||||
|
|
@ -2088,7 +2177,7 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
|
|||
|
||||
/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
|
||||
the auto-vectorizer. */
|
||||
m_BDVER1
|
||||
m_BDVER
|
||||
};
|
||||
|
||||
/* Feature tests against the various architecture variations. */
|
||||
|
|
@ -2125,7 +2214,7 @@ static const unsigned int x86_avx256_split_unaligned_load
|
|||
= m_COREI7 | m_GENERIC;
|
||||
|
||||
static const unsigned int x86_avx256_split_unaligned_store
|
||||
= m_COREI7 | m_BDVER1 | m_GENERIC;
|
||||
= m_COREI7 | m_BDVER | m_GENERIC;
|
||||
|
||||
/* In case the average insn count for single function invocation is
|
||||
lower than this constant, emit fast (but longer) prologue and
|
||||
|
|
@ -2508,6 +2597,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
|
|||
{&generic64_cost, 16, 10, 16, 10, 16},
|
||||
{&amdfam10_cost, 32, 24, 32, 7, 32},
|
||||
{&bdver1_cost, 32, 24, 32, 7, 32},
|
||||
{&bdver2_cost, 32, 24, 32, 7, 32},
|
||||
{&btver1_cost, 32, 24, 32, 7, 32},
|
||||
{&atom_cost, 16, 7, 16, 7, 16}
|
||||
};
|
||||
|
|
@ -2538,6 +2628,7 @@ static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
|
|||
"k8",
|
||||
"amdfam10",
|
||||
"bdver1",
|
||||
"bdver2",
|
||||
"btver1"
|
||||
};
|
||||
|
||||
|
|
@ -2939,6 +3030,12 @@ ix86_option_override_internal (bool main_args_p)
|
|||
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
||||
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
|
||||
| PTA_XOP | PTA_LWP},
|
||||
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
|
||||
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
||||
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
|
||||
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
|
||||
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
|
||||
| PTA_FMA},
|
||||
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC64,
|
||||
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
|
||||
| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16},
|
||||
|
|
@ -21878,6 +21975,7 @@ ix86_issue_rate (void)
|
|||
case PROCESSOR_GENERIC32:
|
||||
case PROCESSOR_GENERIC64:
|
||||
case PROCESSOR_BDVER1:
|
||||
case PROCESSOR_BDVER2:
|
||||
case PROCESSOR_BTVER1:
|
||||
return 3;
|
||||
|
||||
|
|
@ -22066,6 +22164,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
|
|||
case PROCESSOR_K8:
|
||||
case PROCESSOR_AMDFAM10:
|
||||
case PROCESSOR_BDVER1:
|
||||
case PROCESSOR_BDVER2:
|
||||
case PROCESSOR_BTVER1:
|
||||
case PROCESSOR_ATOM:
|
||||
case PROCESSOR_GENERIC32:
|
||||
|
|
@ -34534,7 +34633,8 @@ do_dispatch (rtx insn, int mode)
|
|||
static bool
|
||||
has_dispatch (rtx insn, int action)
|
||||
{
|
||||
if (ix86_tune == PROCESSOR_BDVER1 && flag_dispatch_scheduler)
|
||||
if ((ix86_tune == PROCESSOR_BDVER1 || ix86_tune == PROCESSOR_BDVER2)
|
||||
&& flag_dispatch_scheduler)
|
||||
switch (action)
|
||||
{
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -242,6 +242,7 @@ extern const struct processor_costs ix86_size_cost;
|
|||
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
|
||||
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
|
||||
#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
|
||||
#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
|
||||
#define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1)
|
||||
#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
|
||||
|
||||
|
|
@ -585,6 +586,7 @@ enum target_cpu_default
|
|||
TARGET_CPU_DEFAULT_k8,
|
||||
TARGET_CPU_DEFAULT_amdfam10,
|
||||
TARGET_CPU_DEFAULT_bdver1,
|
||||
TARGET_CPU_DEFAULT_bdver2,
|
||||
TARGET_CPU_DEFAULT_btver1,
|
||||
|
||||
TARGET_CPU_DEFAULT_max
|
||||
|
|
@ -2031,6 +2033,7 @@ enum processor_type
|
|||
PROCESSOR_GENERIC64,
|
||||
PROCESSOR_AMDFAM10,
|
||||
PROCESSOR_BDVER1,
|
||||
PROCESSOR_BDVER2,
|
||||
PROCESSOR_BTVER1,
|
||||
PROCESSOR_ATOM,
|
||||
PROCESSOR_max
|
||||
|
|
|
|||
|
|
@ -369,7 +369,7 @@
|
|||
|
||||
;; Processor type.
|
||||
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
|
||||
atom,generic64,amdfam10,bdver1,btver1"
|
||||
atom,generic64,amdfam10,bdver1,bdver2,btver1"
|
||||
(const (symbol_ref "ix86_schedule")))
|
||||
|
||||
;; A basic instruction type. Refinements due to arguments to be
|
||||
|
|
|
|||
|
|
@ -384,7 +384,7 @@ the function.
|
|||
|
||||
mdispatch-scheduler
|
||||
Target RejectNegative Var(flag_dispatch_scheduler)
|
||||
Do dispatch scheduling if processor is bdver1 and Haifa scheduling
|
||||
Do dispatch scheduling if processor is bdver1 or bdver2 and Haifa scheduling
|
||||
is selected.
|
||||
|
||||
mprefer-avx128
|
||||
|
|
|
|||
Loading…
Reference in New Issue