mips.c (mips_emit_prefetch): Restructure to avoid use of arrays, handle indexed prefetch.
2003-10-03 Chris Demetriou <cgd@broadcom.com> * config/mips/mips.c (mips_emit_prefetch): Restructure to avoid use of arrays, handle indexed prefetch. * config/mips/mips.h (ISA_HAS_FP4, ISA_HAS_PREFETCH): Update comments. (ISA_HAS_PREFETCHX): New deffine. * config/mips/mips.md ("type" attr): Add new "prefetchx" value, update comments. (prefetch_indexed_di, prefetch_indexed_si): New insns. From-SVN: r72077
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@ -1,3 +1,13 @@
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2003-10-03 Chris Demetriou <cgd@broadcom.com>
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* config/mips/mips.c (mips_emit_prefetch): Restructure
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to avoid use of arrays, handle indexed prefetch.
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* config/mips/mips.h (ISA_HAS_FP4, ISA_HAS_PREFETCH): Update comments.
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(ISA_HAS_PREFETCHX): New deffine.
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* config/mips/mips.md ("type" attr): Add new "prefetchx" value,
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update comments.
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(prefetch_indexed_di, prefetch_indexed_si): New insns.
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2003-10-03 Jeff Sturm <jsturm@one-point.com>
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Roger Sayle <roger@eyesopen.com>
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@ -9636,30 +9636,22 @@ mips_use_dfa_pipeline_interface (void)
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const char *
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mips_emit_prefetch (rtx *operands)
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{
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/* For the mips32/64 architectures the hint fields are arranged
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by operation (load/store) and locality (normal/streamed/retained).
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Irritatingly, numbers 2 and 3 are reserved leaving no simple
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algorithm for figuring the hint. */
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int write = INTVAL (operands[1]);
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int locality = INTVAL (operands[2]);
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int indexed = GET_CODE (operands[3]) == REG;
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int code;
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char buffer[30];
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if (locality <= 0)
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code = (write ? 5 : 4); /* store_streamed / load_streamed. */
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else if (locality <= 2)
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code = (write ? 1 : 0); /* store / load. */
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else
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code = (write ? 7 : 6); /* store_retained / load_retained. */
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static const char * const alt[2][4] = {
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{
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"pref\t4,%3(%0)",
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"pref\t0,%3(%0)",
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"pref\t0,%3(%0)",
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"pref\t6,%3(%0)"
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},
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{
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"pref\t5,%3(%0)",
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"pref\t1,%3(%0)",
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"pref\t1,%3(%0)",
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"pref\t7,%3(%0)"
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}
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};
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return alt[write][locality];
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sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
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output_asm_insn (buffer, operands);
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return "";
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}
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@ -823,9 +823,9 @@ extern const struct mips_cpu_info *mips_tune_info;
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|| ISA_MIPS32R2 \
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|| ISA_MIPS64)
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/* This is a catch all for the other new mips4 instructions: indexed load and
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indexed prefetch instructions, the FP madd and msub instructions,
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and the FP recip and recip sqrt instructions */
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/* This is a catch all for other mips4 instructions: indexed load, the
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FP madd and msub instructions, and the FP recip and recip sqrt
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instructions. */
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#define ISA_HAS_FP4 ((ISA_MIPS4 \
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|| ISA_MIPS64) \
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&& !TARGET_MIPS16)
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@ -901,13 +901,21 @@ extern const struct mips_cpu_info *mips_tune_info;
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|| TARGET_SR71K \
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))
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/* ISA has data prefetch instruction. */
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/* ISA has data prefetch instructions. This controls use of 'pref'. */
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#define ISA_HAS_PREFETCH ((ISA_MIPS4 \
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|| ISA_MIPS32 \
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|| ISA_MIPS32R2 \
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|| ISA_MIPS64) \
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&& !TARGET_MIPS16)
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/* ISA has data indexed prefetch instructions. This controls use of
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'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
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(prefx is a cop1x instruction, so can only be used if FP is
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enabled.) */
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#define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
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|| ISA_MIPS64) \
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&& !TARGET_MIPS16)
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/* True if trunc.w.s and trunc.w.d are real (not synthetic)
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instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
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also requires TARGET_DOUBLE_FLOAT. */
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@ -98,7 +98,8 @@
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;; call unconditional call
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;; load load instruction(s)
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;; store store instruction(s)
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;; prefetch memory prefetch
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;; prefetch memory prefetch (register + offset)
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;; prefetchx memory indexed prefetch (register + register)
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;; move data movement within same register set
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;; condmove conditional moves
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;; xfer transfer to/from coprocessor
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@ -123,7 +124,7 @@
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;; multi multiword sequence (or user asm statements)
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;; nop no operation
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(define_attr "type"
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"unknown,branch,jump,call,load,store,prefetch,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
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"unknown,branch,jump,call,load,store,prefetch,prefetchx,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
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(cond [(eq_attr "jal" "!unset")
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(const_string "call")]
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(const_string "unknown")))
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@ -8513,6 +8514,15 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j\t%2%/"
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{ return mips_emit_prefetch (operands); }
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[(set_attr "type" "prefetch")])
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(define_insn "prefetch_indexed_si"
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[(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 3 "register_operand" "r"))
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(match_operand:SI 1 "const_int_operand" "n")
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(match_operand:SI 2 "const_int_operand" "n"))]
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"ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == SImode"
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{ return mips_emit_prefetch (operands); }
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[(set_attr "type" "prefetchx")])
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(define_insn "prefetch_si"
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[(prefetch (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "const_int_operand" "n")
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@ -8533,6 +8543,15 @@ ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j\t%2%/"
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{ return mips_emit_prefetch (operands); }
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[(set_attr "type" "prefetch")])
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(define_insn "prefetch_indexed_di"
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[(prefetch (plus:DI (match_operand:DI 0 "register_operand" "r")
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(match_operand:DI 3 "register_operand" "r"))
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(match_operand:DI 1 "const_int_operand" "n")
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(match_operand:DI 2 "const_int_operand" "n"))]
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"ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && Pmode == DImode"
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{ return mips_emit_prefetch (operands); }
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[(set_attr "type" "prefetchx")])
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(define_insn "prefetch_di"
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[(prefetch (match_operand:DI 0 "register_operand" "r")
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(match_operand:DI 1 "const_int_operand" "n")
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