thunderx2t99.md (thunderx2t99_ls_both): Delete.
2018-05-17 Steve Ellcey <sellcey@cavium.com> * config/aarch64/thunderx2t99.md (thunderx2t99_ls_both): Delete. (thunderx2t99_multiple): Delete psuedo-units from used cpus. Add untyped. (thunderx2t99_alu_shift): Remove alu_shift_reg, alus_shift_reg. Change logics_shift_reg to logics_shift_imm. (thunderx2t99_fp_loadpair_basic): Delete. (thunderx2t99_fp_storepair_basic): Delete. (thunderx2t99_asimd_int): Add neon_sub and neon_sub_q types. (thunderx2t99_asimd_polynomial): Delete. (thunderx2t99_asimd_fp_simple): Add neon_fp_mul_s_scalar_q and neon_fp_mul_d_scalar_q. (thunderx2t99_asimd_fp_conv): Add *int_to_fp* types. (thunderx2t99_asimd_misc): Delete neon_dup and neon_dup_q. (thunderx2t99_asimd_recip_step): Add missing *sqrt* types. (thunderx2t99_asimd_lut): Add missing tbl types. (thunderx2t99_asimd_ext): Delete. (thunderx2t99_asimd_load1_1_mult): Delete. (thunderx2t99_asimd_load1_2_mult): Delete. (thunderx2t99_asimd_load1_ldp): New. (thunderx2t99_asimd_load1): New. (thunderx2t99_asimd_load2): Add missing *load2* types. (thunderx2t99_asimd_load3): New. (thunderx2t99_asimd_load4): New. (thunderx2t99_asimd_store1_1_mult): Delete. (thunderx2t99_asimd_store1_2_mult): Delete. (thunderx2t99_asimd_store2_mult): Delete. (thunderx2t99_asimd_store2_onelane): Delete. (thunderx2t99_asimd_store_stp): New. (thunderx2t99_asimd_store1): New. (thunderx2t99_asimd_store2): New. (thunderx2t99_asimd_store3): New. (thunderx2t99_asimd_store4): New. From-SVN: r260335
This commit is contained in:
parent
fcf4f8311e
commit
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@ -1,3 +1,38 @@
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2018-05-17 Steve Ellcey <sellcey@cavium.com>
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* config/aarch64/thunderx2t99.md (thunderx2t99_ls_both): Delete.
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(thunderx2t99_multiple): Delete psuedo-units from used cpus.
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Add untyped.
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(thunderx2t99_alu_shift): Remove alu_shift_reg, alus_shift_reg.
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Change logics_shift_reg to logics_shift_imm.
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(thunderx2t99_fp_loadpair_basic): Delete.
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(thunderx2t99_fp_storepair_basic): Delete.
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(thunderx2t99_asimd_int): Add neon_sub and neon_sub_q types.
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(thunderx2t99_asimd_polynomial): Delete.
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(thunderx2t99_asimd_fp_simple): Add neon_fp_mul_s_scalar_q
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and neon_fp_mul_d_scalar_q.
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(thunderx2t99_asimd_fp_conv): Add *int_to_fp* types.
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(thunderx2t99_asimd_misc): Delete neon_dup and neon_dup_q.
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(thunderx2t99_asimd_recip_step): Add missing *sqrt* types.
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(thunderx2t99_asimd_lut): Add missing tbl types.
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(thunderx2t99_asimd_ext): Delete.
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(thunderx2t99_asimd_load1_1_mult): Delete.
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(thunderx2t99_asimd_load1_2_mult): Delete.
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(thunderx2t99_asimd_load1_ldp): New.
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(thunderx2t99_asimd_load1): New.
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(thunderx2t99_asimd_load2): Add missing *load2* types.
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(thunderx2t99_asimd_load3): New.
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(thunderx2t99_asimd_load4): New.
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(thunderx2t99_asimd_store1_1_mult): Delete.
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(thunderx2t99_asimd_store1_2_mult): Delete.
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(thunderx2t99_asimd_store2_mult): Delete.
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(thunderx2t99_asimd_store2_onelane): Delete.
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(thunderx2t99_asimd_store_stp): New.
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(thunderx2t99_asimd_store1): New.
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(thunderx2t99_asimd_store2): New.
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(thunderx2t99_asimd_store3): New.
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(thunderx2t99_asimd_store4): New.
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2018-05-17 Jerome Lambourg <lambourg@adacore.com>
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* config/arm/arm_cmse.h (cmse_nsfptr_create, cmse_is_nsfptr): Remove
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@ -54,8 +54,6 @@
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(define_reservation "thunderx2t99_ls01" "thunderx2t99_ls0|thunderx2t99_ls1")
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(define_reservation "thunderx2t99_f01" "thunderx2t99_f0|thunderx2t99_f1")
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(define_reservation "thunderx2t99_ls_both" "thunderx2t99_ls0+thunderx2t99_ls1")
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; A load with delay in the ls0/ls1 pipes.
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(define_reservation "thunderx2t99_l0delay" "thunderx2t99_ls0,\
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thunderx2t99_ls0d1,thunderx2t99_ls0d2,\
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@ -86,12 +84,10 @@
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(define_insn_reservation "thunderx2t99_multiple" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "multiple"))
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(eq_attr "type" "multiple,untyped"))
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"thunderx2t99_i0+thunderx2t99_i1+thunderx2t99_i2+thunderx2t99_ls0+\
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thunderx2t99_ls1+thunderx2t99_sd+thunderx2t99_i1m1+thunderx2t99_i1m2+\
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thunderx2t99_i1m3+thunderx2t99_ls0d1+thunderx2t99_ls0d2+thunderx2t99_ls0d3+\
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thunderx2t99_ls1d1+thunderx2t99_ls1d2+thunderx2t99_ls1d3+thunderx2t99_f0+\
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thunderx2t99_f1")
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thunderx2t99_i1m3+thunderx2t99_f0+thunderx2t99_f1")
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;; Integer arithmetic/logic instructions.
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@ -113,9 +109,9 @@
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(define_insn_reservation "thunderx2t99_alu_shift" 2
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "alu_shift_imm,alu_ext,alu_shift_reg,\
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alus_shift_imm,alus_ext,alus_shift_reg,\
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logic_shift_imm,logics_shift_reg"))
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(eq_attr "type" "alu_shift_imm,alu_ext,\
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alus_shift_imm,alus_ext,\
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logic_shift_imm,logics_shift_imm"))
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"thunderx2t99_i012,thunderx2t99_i012")
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(define_insn_reservation "thunderx2t99_div" 13
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@ -228,21 +224,11 @@
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(eq_attr "type" "f_loads,f_loadd"))
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"thunderx2t99_ls01")
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(define_insn_reservation "thunderx2t99_fp_loadpair_basic" 4
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_load1_2reg"))
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"thunderx2t99_ls01*2")
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(define_insn_reservation "thunderx2t99_fp_store_basic" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "f_stores,f_stored"))
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"thunderx2t99_ls01,thunderx2t99_sd")
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(define_insn_reservation "thunderx2t99_fp_storepair_basic" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_store1_2reg"))
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"thunderx2t99_ls01,(thunderx2t99_ls01+thunderx2t99_sd),thunderx2t99_sd")
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;; ASIMD integer instructions.
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(define_insn_reservation "thunderx2t99_asimd_int" 7
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neon_arith_acc,neon_arith_acc_q,\
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neon_abs,neon_abs_q,\
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neon_add,neon_add_q,\
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neon_sub,neon_sub_q,\
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neon_neg,neon_neg_q,\
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neon_add_long,neon_add_widen,\
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neon_add_halve,neon_add_halve_q,\
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(eq_attr "type" "neon_logic,neon_logic_q"))
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"thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_polynomial" 5
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_mul_d_long"))
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"thunderx2t99_f01")
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;; ASIMD floating-point instructions.
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(define_insn_reservation "thunderx2t99_asimd_fp_simple" 5
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neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q,\
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neon_fp_mul_s,neon_fp_mul_d,\
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neon_fp_mul_s_q,neon_fp_mul_d_q,\
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neon_fp_mul_s_scalar_q,neon_fp_mul_d_scalar_q,\
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neon_fp_mla_s,neon_fp_mla_d,\
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neon_fp_mla_s_q,neon_fp_mla_d_q"))
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"thunderx2t99_f01")
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@ -341,6 +324,8 @@
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(eq_attr "type" "neon_fp_cvt_widen_s,neon_fp_cvt_narrow_d_q,\
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neon_fp_to_int_s,neon_fp_to_int_d,\
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neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
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neon_int_to_fp_s,neon_int_to_fp_d,\
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neon_int_to_fp_s_q,neon_int_to_fp_d_q,\
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neon_fp_round_s,neon_fp_round_d,\
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neon_fp_round_s_q,neon_fp_round_d_q"))
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"thunderx2t99_f01")
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neon_fp_recpx_s,neon_fp_recpx_d,\
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neon_fp_recpx_s_q,neon_fp_recpx_d_q,\
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neon_rev,neon_rev_q,\
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neon_dup,neon_dup_q,\
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neon_permute,neon_permute_q"))
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"thunderx2t99_f01")
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q,\
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neon_fp_recps_d,neon_fp_recps_d_q,\
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neon_fp_sqrt_s,neon_fp_sqrt_s_q,\
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neon_fp_sqrt_d,neon_fp_sqrt_d_q,\
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neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\
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neon_fp_rsqrte_d, neon_fp_rsqrte_d_q,\
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neon_fp_rsqrts_s, neon_fp_rsqrts_s_q,\
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neon_fp_rsqrts_d, neon_fp_rsqrts_d_q"))
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"thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_lut" 8
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_tbl1,neon_tbl1_q,neon_tbl2_q"))
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(eq_attr "type" "neon_tbl1,neon_tbl1_q,neon_tbl2,neon_tbl2_q,\
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neon_tbl3,neon_tbl3_q,neon_tbl4,neon_tbl4_q"))
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"thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_elt_to_gr" 6
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(eq_attr "type" "neon_to_gp,neon_to_gp_q"))
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"thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_ext" 7
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_shift_imm_narrow_q,neon_sat_shift_imm_narrow_q"))
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"thunderx2t99_f01")
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;; ASIMD load instructions.
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; NOTE: These reservations attempt to model latency and throughput correctly,
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; but the cycle timing of unit allocation is not necessarily accurate (because
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; insns are split into uops, and those may be issued out-of-order).
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(define_insn_reservation "thunderx2t99_asimd_load1_1_mult" 4
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(define_insn_reservation "thunderx2t99_asimd_load1_ldp" 5
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q"))
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"thunderx2t99_ls01")
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(eq_attr "type" "neon_ldp,neon_ldp_q"))
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"thunderx2t99_i012,thunderx2t99_ls01")
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(define_insn_reservation "thunderx2t99_asimd_load1_2_mult" 4
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(define_insn_reservation "thunderx2t99_asimd_load1" 4
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q"))
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"thunderx2t99_ls_both")
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(eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q,\
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neon_load1_2reg,neon_load1_2reg_q,\
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neon_load1_3reg,neon_load1_3reg_q,\
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neon_load1_4reg,neon_load1_4reg_q"))
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"thunderx2t99_ls01")
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(define_insn_reservation "thunderx2t99_asimd_load1_onelane" 5
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_load2_2reg,neon_load2_2reg_q,\
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neon_load2_one_lane,neon_load2_one_lane_q,\
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neon_load2_all_lanes,neon_load2_all_lanes_q"))
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"(thunderx2t99_l0delay,thunderx2t99_f01)|(thunderx2t99_l1delay,\
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thunderx2t99_f01)")
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"thunderx2t99_l01delay,thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_load3" 7
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q,\
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neon_load3_one_lane,neon_load3_one_lane_q,\
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neon_load3_all_lanes,neon_load3_all_lanes_q"))
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"thunderx2t99_l01delay,thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_load4" 8
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_load4_4reg,neon_load4_4reg_q,\
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neon_load4_one_lane,neon_load4_one_lane_q,\
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neon_load4_all_lanes,neon_load4_all_lanes_q"))
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"thunderx2t99_l01delay,thunderx2t99_f01")
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;; ASIMD store instructions.
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; Same note applies as for ASIMD load instructions.
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(define_insn_reservation "thunderx2t99_asimd_store1_1_mult" 1
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(define_insn_reservation "thunderx2t99_asimd_store_stp" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q"))
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"thunderx2t99_ls01")
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(eq_attr "type" "neon_stp,neon_stp_q"))
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"thunderx2t99_ls01,thunderx2t99_sd")
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(define_insn_reservation "thunderx2t99_asimd_store1_2_mult" 1
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(define_insn_reservation "thunderx2t99_asimd_store1" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_store1_2reg,neon_store1_2reg_q"))
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"thunderx2t99_ls_both")
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(eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
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neon_store1_2reg,neon_store1_2reg_q,\
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neon_store1_3reg,neon_store1_4reg"))
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"thunderx2t99_ls01")
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(define_insn_reservation "thunderx2t99_asimd_store1_onelane" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_store1_one_lane,neon_store1_one_lane_q"))
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"thunderx2t99_ls01,thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_store2_mult" 1
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(define_insn_reservation "thunderx2t99_asimd_store2" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_store2_2reg,neon_store2_2reg_q"))
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"thunderx2t99_ls_both,thunderx2t99_f01")
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(eq_attr "type" "neon_store2_2reg,neon_store2_2reg_q,\
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neon_store2_one_lane,neon_store2_one_lane_q"))
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"thunderx2t99_ls01,thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_store2_onelane" 1
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(define_insn_reservation "thunderx2t99_asimd_store3" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_store2_one_lane,neon_store2_one_lane_q"))
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(eq_attr "type" "neon_store3_3reg,neon_store3_3reg_q,\
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neon_store3_one_lane,neon_store3_one_lane_q"))
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"thunderx2t99_ls01,thunderx2t99_f01")
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(define_insn_reservation "thunderx2t99_asimd_store4" 1
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(and (eq_attr "tune" "thunderx2t99")
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(eq_attr "type" "neon_store4_4reg,neon_store4_4reg_q,\
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neon_store4_one_lane,neon_store4_one_lane_q"))
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"thunderx2t99_ls01,thunderx2t99_f01")
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;; Crypto extensions.
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