amdgcn: Vector procedure call ABI
Adjust the (unofficial) procedure calling ABI such that vector arguments are passed in vector registers, not on the stack. Scalar arguments continue to be passed in scalar registers, making a total of 12 argument registers. The return value is also moved to a vector register (even for scalars; it would be possible to retain the scalar location, using untyped_call, but there's no obvious advantage in doing so). After this change the ABI is as follows: s0-s13 : Reserved for kernel launch parameters. s14-s15 : Frame pointer. s16-s17 : Stack pointer. s18-s19 : Link register. s20-s21 : Exec Save. s22-s23 : CC Save. s24-s25 : Scalar arguments. NO LONGER RETURN VALUE. s26-s29 : Additional scalar arguments (makes 6 total). s30-s31 : Static Chain. v0 : Prologue/epilogue scratch. v1 : Constant 0, 1, 2, 3, 4, ... 63. v2-v7 : Prologue/epilogue scratch. v8-v9 : Return value & vector arguments. NEW. v10-v13 : Additional vector arguments (makes 6 total). NEW. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_function_value): Allow vector return values. (num_arg_regs): Allow vector arguments. (gcn_function_arg): Likewise. (gcn_function_arg_advance): Likewise. (gcn_arg_partial_bytes): Likewise. (gcn_return_in_memory): Likewise. (gcn_expand_epilogue): Get return value from v8. * config/gcn/gcn.h (RETURN_VALUE_REG): Set to v8. (FIRST_PARM_REG): USE FIRST_SGPR_REG for clarity. (FIRST_VPARM_REG): New. (FUNCTION_ARG_REGNO_P): Allow vector parameters. (struct gcn_args): Add vnum field. (LIBCALL_VALUE): All vector return values. * config/gcn/gcn.md (gcn_call_value): Add vector constraints. (gcn_call_value_indirect): Likewise.
This commit is contained in:
Andrew Stubbs
parent
9aa08cd484
commit
4e1914625d
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@ -2284,7 +2284,7 @@ gcn_function_value (const_tree valtype, const_tree, bool)
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&& GET_MODE_SIZE (mode) < 4)
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mode = SImode;
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return gen_rtx_REG (mode, SGPR_REGNO (RETURN_VALUE_REG));
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return gen_rtx_REG (mode, RETURN_VALUE_REG);
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}
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/* Implement TARGET_FUNCTION_VALUE_REGNO_P.
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@ -2308,7 +2308,9 @@ num_arg_regs (const function_arg_info &arg)
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return 0;
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int size = arg.promoted_size_in_bytes ();
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return (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
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int regsize = UNITS_PER_WORD * (VECTOR_MODE_P (arg.mode)
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? GET_MODE_NUNITS (arg.mode) : 1);
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return (size + regsize - 1) / regsize;
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}
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/* Implement TARGET_STRICT_ARGUMENT_NAMING.
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@ -2358,16 +2360,16 @@ gcn_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
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if (targetm.calls.must_pass_in_stack (arg))
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return 0;
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/* Vector parameters are not supported yet. */
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if (VECTOR_MODE_P (arg.mode))
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return 0;
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int reg_num = FIRST_PARM_REG + cum->num;
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int first_reg = (VECTOR_MODE_P (arg.mode)
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? FIRST_VPARM_REG : FIRST_PARM_REG);
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int cum_num = (VECTOR_MODE_P (arg.mode)
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? cum->vnum : cum->num);
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int reg_num = first_reg + cum_num;
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int num_regs = num_arg_regs (arg);
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if (num_regs > 0)
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while (reg_num % num_regs != 0)
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reg_num++;
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if (reg_num + num_regs <= FIRST_PARM_REG + NUM_PARM_REGS)
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if (reg_num + num_regs <= first_reg + NUM_PARM_REGS)
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return gen_rtx_REG (arg.mode, reg_num);
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}
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else
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@ -2419,11 +2421,15 @@ gcn_function_arg_advance (cumulative_args_t cum_v,
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if (!arg.named)
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return;
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int first_reg = (VECTOR_MODE_P (arg.mode)
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? FIRST_VPARM_REG : FIRST_PARM_REG);
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int *cum_num = (VECTOR_MODE_P (arg.mode)
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? &cum->vnum : &cum->num);
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int num_regs = num_arg_regs (arg);
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if (num_regs > 0)
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while ((FIRST_PARM_REG + cum->num) % num_regs != 0)
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cum->num++;
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cum->num += num_regs;
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while ((first_reg + *cum_num) % num_regs != 0)
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(*cum_num)++;
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*cum_num += num_regs;
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}
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else
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{
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@ -2454,14 +2460,18 @@ gcn_arg_partial_bytes (cumulative_args_t cum_v, const function_arg_info &arg)
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if (targetm.calls.must_pass_in_stack (arg))
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return 0;
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if (cum->num >= NUM_PARM_REGS)
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int cum_num = (VECTOR_MODE_P (arg.mode) ? cum->vnum : cum->num);
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int regsize = UNITS_PER_WORD * (VECTOR_MODE_P (arg.mode)
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? GET_MODE_NUNITS (arg.mode) : 1);
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if (cum_num >= NUM_PARM_REGS)
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return 0;
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/* If the argument fits entirely in registers, return 0. */
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if (cum->num + num_arg_regs (arg) <= NUM_PARM_REGS)
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if (cum_num + num_arg_regs (arg) <= NUM_PARM_REGS)
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return 0;
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return (NUM_PARM_REGS - cum->num) * UNITS_PER_WORD;
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return (NUM_PARM_REGS - cum_num) * regsize;
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}
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/* A normal function which takes a pointer argument (to a scalar) may be
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@ -2549,14 +2559,11 @@ gcn_return_in_memory (const_tree type, const_tree ARG_UNUSED (fntype))
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if (AGGREGATE_TYPE_P (type))
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return true;
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/* Vector return values are not supported yet. */
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if (VECTOR_TYPE_P (type))
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return true;
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if (mode == BLKmode)
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return true;
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if (size > 2 * UNITS_PER_WORD)
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if ((!VECTOR_TYPE_P (type) && size > 2 * UNITS_PER_WORD)
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|| size > 2 * UNITS_PER_WORD * 64)
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return true;
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return false;
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@ -3199,9 +3206,10 @@ gcn_expand_epilogue (void)
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emit_move_insn (kernarg_reg, retptr_mem);
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rtx retval_mem = gen_rtx_MEM (SImode, kernarg_reg);
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rtx scalar_retval = gen_rtx_REG (SImode, FIRST_PARM_REG);
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set_mem_addr_space (retval_mem, ADDR_SPACE_SCALAR_FLAT);
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emit_move_insn (retval_mem,
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gen_rtx_REG (SImode, SGPR_REGNO (RETURN_VALUE_REG)));
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emit_move_insn (scalar_retval, gen_rtx_REG (SImode, RETURN_VALUE_REG));
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emit_move_insn (retval_mem, scalar_retval);
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}
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emit_jump_insn (gen_gcn_return ());
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@ -138,7 +138,7 @@
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#define LINK_REGNUM 18
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#define EXEC_SAVE_REG 20
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#define CC_SAVE_REG 22
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#define RETURN_VALUE_REG 24 /* Must be divisible by 4. */
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#define RETURN_VALUE_REG 168 /* Must be divisible by 4. */
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#define STATIC_CHAIN_REGNUM 30
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#define WORK_ITEM_ID_Z_REG 162
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#define SOFT_ARG_REG 416
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@ -146,7 +146,8 @@
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#define DWARF_LINK_REGISTER 420
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#define FIRST_PSEUDO_REGISTER 421
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#define FIRST_PARM_REG 24
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#define FIRST_PARM_REG (FIRST_SGPR_REG + 24)
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#define FIRST_VPARM_REG (FIRST_VGPR_REG + 8)
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#define NUM_PARM_REGS 6
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/* There is no arg pointer. Just choose random fixed register that does
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@ -164,7 +165,8 @@
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#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
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#define CC_REGNO_P(X) ((X) == SCC_REG || (X) == VCC_REG)
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#define FUNCTION_ARG_REGNO_P(N) \
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((N) >= FIRST_PARM_REG && (N) < (FIRST_PARM_REG + NUM_PARM_REGS))
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(((N) >= FIRST_PARM_REG && (N) < (FIRST_PARM_REG + NUM_PARM_REGS)) \
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|| ((N) >= FIRST_VPARM_REG && (N) < (FIRST_VPARM_REG + NUM_PARM_REGS)))
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#define FIXED_REGISTERS { \
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@ -550,6 +552,7 @@ typedef struct gcn_args
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tree fntype;
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struct gcn_kernel_args args;
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int num;
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int vnum;
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int offset;
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int alignment;
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} CUMULATIVE_ARGS;
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@ -653,7 +656,7 @@ enum gcn_builtin_codes
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}
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/* This needs to match gcn_function_value. */
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#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, SGPR_REGNO (RETURN_VALUE_REG))
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#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RETURN_VALUE_REG)
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/* The s_ff0 and s_flbit instructions return -1 if no input bits are set. */
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#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
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@ -908,11 +908,11 @@
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{})
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(define_insn "gcn_call_value"
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[(set (match_operand 0 "register_operand" "=Sg,Sg")
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(call (mem (match_operand 1 "immediate_operand" "Y,B"))
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[(set (match_operand 0 "register_operand" "=Sgv,Sgv")
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(call (mem (match_operand 1 "immediate_operand" " Y, B"))
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(match_operand 2 "const_int_operand")))
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(clobber (reg:DI LR_REGNUM))
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(clobber (match_scratch:DI 3 "=&Sg,X"))]
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(clobber (match_scratch:DI 3 "=&Sg, X"))]
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""
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"@
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s_getpc_b64\t%3\;s_add_u32\t%L3, %L3, %1@rel32@lo+4\;s_addc_u32\t%H3, %H3, %1@rel32@hi+4\;s_swappc_b64\ts[18:19], %3
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@ -921,11 +921,11 @@
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(set_attr "length" "24")])
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(define_insn "gcn_call_value_indirect"
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[(set (match_operand 0 "register_operand" "=Sg")
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(call (mem (match_operand:DI 1 "register_operand" "Sg"))
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[(set (match_operand 0 "register_operand" "=Sgv")
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(call (mem (match_operand:DI 1 "register_operand" " Sg"))
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(match_operand 2 "" "")))
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(clobber (reg:DI LR_REGNUM))
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(clobber (match_scratch:DI 3 "=X"))]
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(clobber (match_scratch:DI 3 "= X"))]
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""
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"s_swappc_b64\ts[18:19], %1"
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[(set_attr "type" "sop1")
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