linux.h: Add #undef for SUBTARGET_CPP_SPEC.
2002-07-03 Eric Christopher <echristo@redhat.com> * config/mips/linux.h: Add #undef for SUBTARGET_CPP_SPEC. * config/mips/mips.h: Remove deprecated -m<processor> options and cc1_cpu_spec associated. (CONSTANT_ADDRESS_P): Fix last patch. (ASM_DECLARE_FUNCTION_NAME): Declare. Fix comment. * config/mips/mips.md (bungt, bunge, sungt_df, sungt_sf, sunge_df, sunge_sf): Remove. From-SVN: r55233
This commit is contained in:
Eric Christopher
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ec4d88f907
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4e314d1fde
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@ -1,3 +1,13 @@
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2002-07-03 Eric Christopher <echristo@redhat.com>
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* config/mips/linux.h: Add #undef for SUBTARGET_CPP_SPEC.
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* config/mips/mips.h: Remove deprecated -m<processor> options
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and cc1_cpu_spec associated.
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(CONSTANT_ADDRESS_P): Fix last patch.
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(ASM_DECLARE_FUNCTION_NAME): Declare. Fix comment.
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* config/mips/mips.md (bungt, bunge, sungt_df, sungt_sf, sunge_df,
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sunge_sf): Remove.
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2002-07-03 Stan Shebs <shebs@apple.com>
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* config/darwin.h (APPLE_CC): Remove, not meaningful in FSF GCC.
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@ -100,7 +110,7 @@ Wed Jul 3 10:24:16 2002 J"orn Rennecke <joern.rennecke@superh.com>
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* cpptrad.c: Update comment.
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2002-07-02 Neil Booth <neil@daikokuya.co.uk>
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* doc/cpp.texi: Update for traditional preprocessing changes.
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* goc/cppopts.texi: Similarly.
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@ -118,7 +128,7 @@ Tue Jul 2 18:45:45 2002 J"orn Rennecke <joern.rennecke@superh.com>
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* sh.c (print_operand, case 'N'): Allow zero vector.
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(arith_reg_or_0_operand): Likewise.
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(zero_vec_operand): Check for CONST_VECTOR, not PARALLEL.
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* sh.h (CONST_COSTS): 0 has 0 cost. Check OUTER_CODE for
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* sh.h (CONST_COSTS): 0 has 0 cost. Check OUTER_CODE for
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IOR, XOR, PLUS and SET and take their respective constant
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ranges into account.
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(PREDICATE_CODES, arith_reg_or_0_operand): Can be CONST_VECTOR.
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@ -290,7 +300,7 @@ Fri Jun 28 17:22:37 2002 Denis Chertykov <denisc@overta.ru>
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Alan Lehotsky <apl@alum.mit.edu>
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Bernd Schmidt <bernds@redhat.com>
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Graham Stott <grahams@redhat.com>
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* doc/extend.texi: Add ip2k port to description of attribute
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naked.
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* doc/install.texi (Specific): Add ip2k description.
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@ -411,7 +421,7 @@ Fri Jun 28 17:22:37 2002 Denis Chertykov <denisc@overta.ru>
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* config/m68hc11/m68hc11.md ("*addsi3"): Use 'o' constraint to
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avoid the auto increment addressing modes.
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("*subsi3"): Likewise.
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(split for add/sub on address): For 68HC12 push the value on
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(split for add/sub on address): For 68HC12 push the value on
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the stack and do the operation with a pop.
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2002-06-28 Neil Booth <neil@daikokuya.co.uk>
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@ -512,7 +522,7 @@ Fri Jun 28 17:22:37 2002 Denis Chertykov <denisc@overta.ru>
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2002-06-27 Daniel Berlin <dberlin@dberlin.org>
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* gcse.c (hoist_code): Rewrite to only get list of dominated
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blocks once per BB. Also fix reversed test (by removing need for
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blocks once per BB. Also fix reversed test (by removing need for
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the test at all).
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2002-06-27 Neil Booth <neil@daikokuya.co.uk>
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@ -587,7 +597,7 @@ Tue Jun 25 21:51:13 2002 J"orn Rennecke <joern.rennecke@superh.com>
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* optabs.c (expand_vector_binop, expand_vector_unop): Don't assume
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GET_MODE_UNIT_SIZE (mode) == UNITS_PER_WORD.
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* config/sh/lib1funcs.asm (udivdi3): Make first divide step
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* config/sh/lib1funcs.asm (udivdi3): Make first divide step
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produce a 32 bit result before normalization, then normalize with a
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left shift. Compute approximative error of 2nd reciprocal
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approximation in 2's complement. Fix mask generation from upper
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@ -644,7 +654,7 @@ Mon Jun 24 21:05:09 2002 J"orn Rennecke <joern.rennecke@superh.com>
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* doc/extend.texi: Change `@dots{}' to `/* @r{@dots{}} */'
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in examples.
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2002-06-24 Art Haas <ahaas@neosoft.com>
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* doc/extend.texi (Other Builtins): Change `...' to `@dots{}'.
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@ -1010,7 +1020,7 @@ Thu Jun 20 12:14:01 CEST 2002 Jan Hubicka <jh@suse.cz>
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* i386.md (xorqi_1_slp, xorqi_2_slp): New patterns.
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2002-06-16 Aldy Hernandez <aldyh@redhat.com>
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* gcc.c-torture/execute/simd-1.c: New.
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* gcc.dg/simd-1.c: New.
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@ -1040,7 +1050,7 @@ Thu Jun 20 12:14:01 CEST 2002 Jan Hubicka <jh@suse.cz>
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(expand_unop): Open-code vector unops.
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(expand_vector_binop): New.
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(expand_vector_unop): New.
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* c-typeck.c (build_binary_op): Allow vectors in binops.
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Allow vectors in conditional operatiors.
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(build_unary_op): Allow vectors in unary minus.
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@ -171,6 +171,7 @@ void FN () \
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builtin_define ("_MIPS_SZINT=32"); \
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} while (0)
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#undef SUBTARGET_CPP_SPEC
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#define SUBTARGET_CPP_SPEC "\
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%{fno-PIC:-U__PIC__ -U__pic__} %{fno-pic:-U__PIC__ -U__pic__} \
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%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} \
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@ -561,10 +561,6 @@ extern void sbss_section PARAMS ((void));
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N_("Work around early 4300 hardware bug")}, \
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{"no-fix4300", -MASK_4300_MUL_FIX, \
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N_("Don't work around early 4300 hardware bug")}, \
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{"3900", 0, \
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N_("Optimize for 3900")}, \
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{"4650", 0, \
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N_("Optimize for 4650")}, \
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{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
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N_("Trap on integer divide by zero")}, \
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{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
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@ -1044,16 +1040,6 @@ extern int mips_abi;
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#define SUBTARGET_CC1_SPEC ""
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#endif
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/* Deal with historic options. */
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#ifndef CC1_CPU_SPEC
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#define CC1_CPU_SPEC "\
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%{!mcpu*: \
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%{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
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%n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
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%{m4650:-march=r4650 -mmad -msingle-float \
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%n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
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#endif
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/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
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/* Note, we will need to adjust the following if we ever find a MIPS variant
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that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
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@ -1073,8 +1059,7 @@ extern int mips_abi;
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%{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
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%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
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%{save-temps: } \
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%(subtarget_cc1_spec) \
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%(cc1_cpu_spec)"
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%(subtarget_cc1_spec)"
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#endif
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/* Preprocessor specs. */
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@ -1099,7 +1084,6 @@ extern int mips_abi;
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#define EXTRA_SPECS \
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{ "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
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{ "cc1_cpu_spec", CC1_CPU_SPEC}, \
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{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
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{ "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
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{ "gas_asm_spec", GAS_ASM_SPEC }, \
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@ -2989,9 +2973,10 @@ typedef struct mips_args {
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|| GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
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|| (GET_CODE (X) == CONST \
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&& ! (flag_pic && pic_address_needs_scratch (X)) \
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&& (!TARGET_GAS) \
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&& (mips_abi == ABI_N32 \
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|| mips_abi == ABI_64)))
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&& (TARGET_GAS) \
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&& (mips_abi != ABI_N32 \
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&& mips_abi != ABI_64)))
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/* Define this, so that when PIC, reload won't try to reload invalid
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addresses which require two reload registers. */
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@ -4275,11 +4260,12 @@ do { \
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/* This is how to declare a function name. The actual work of
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emitting the label is moved to function_prologue, so that we can
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get the line number correctly emitted before the .ent directive,
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and after any .file directives. */
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/*
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and after any .file directives. Define to NULL so that the function
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is not declared before the .ent directive elsewhere. */
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#undef ASM_DECLARE_FUNCTION_NAME
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#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
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*/
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/* This is how to output an internal numbered label where
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PREFIX is the class of label and NUM is the number within the class. */
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@ -8095,22 +8095,6 @@ move\\t%0,%z4\\n\\
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}
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}")
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(define_expand "bungt"
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[(set (pc)
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(if_then_else (ungt:CC (cc0)
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"
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{
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if (operands[0]) /* avoid unused code warning */
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{
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gen_conditional_branch (operands, UNGT);
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DONE;
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}
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}")
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(define_expand "bunlt"
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[(set (pc)
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(if_then_else (unlt:CC (cc0)
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@ -8143,22 +8127,6 @@ move\\t%0,%z4\\n\\
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}
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}")
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(define_expand "bunge"
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[(set (pc)
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(if_then_else (unge:CC (cc0)
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(const_int 0))
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"
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{
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if (operands[0]) /* avoid unused code warning */
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{
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gen_conditional_branch (operands, UNGE);
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DONE;
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}
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}")
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(define_expand "bunle"
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[(set (pc)
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(if_then_else (unle:CC (cc0)
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@ -9255,18 +9223,6 @@ move\\t%0,%z4\\n\\
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sungt_df"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(ungt:CC (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"*
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{
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return mips_fill_delay_slot (\"c.ugt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
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}"
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sunlt_df"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(unlt:CC (match_operand:DF 1 "register_operand" "f")
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@ -9291,18 +9247,6 @@ move\\t%0,%z4\\n\\
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sunge_df"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(unge:CC (match_operand:DF 1 "register_operand" "f")
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(match_operand:DF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"*
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{
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return mips_fill_delay_slot (\"c.uge.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
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}"
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sunle_df"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(unle:CC (match_operand:DF 1 "register_operand" "f")
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@ -9399,18 +9343,6 @@ move\\t%0,%z4\\n\\
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sungt_sf"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(ungt:CC (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"*
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{
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return mips_fill_delay_slot (\"c.ugt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
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}"
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sunlt_sf"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(unlt:CC (match_operand:SF 1 "register_operand" "f")
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@ -9435,18 +9367,6 @@ move\\t%0,%z4\\n\\
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sunge_sf"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(unge:CC (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
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"*
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{
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return mips_fill_delay_slot (\"c.uge.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
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}"
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[(set_attr "type" "fcmp")
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(set_attr "mode" "FPSW")])
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(define_insn "sunle_sf"
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[(set (match_operand:CC 0 "register_operand" "=z")
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(unle:CC (match_operand:SF 1 "register_operand" "f")
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