linux.h: Add #undef for SUBTARGET_CPP_SPEC.

2002-07-03  Eric Christopher  <echristo@redhat.com>

	* config/mips/linux.h: Add #undef for SUBTARGET_CPP_SPEC.
	* config/mips/mips.h: Remove deprecated -m<processor> options
	and cc1_cpu_spec associated.
	(CONSTANT_ADDRESS_P): Fix last patch.
	(ASM_DECLARE_FUNCTION_NAME): Declare. Fix comment.
	* config/mips/mips.md (bungt, bunge, sungt_df, sungt_sf, sunge_df,
	sunge_sf): Remove.

From-SVN: r55233
This commit is contained in:
Eric Christopher 2002-07-04 05:03:02 +00:00
parent ec4d88f907
commit 4e314d1fde
4 changed files with 29 additions and 112 deletions

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@ -1,3 +1,13 @@
2002-07-03 Eric Christopher <echristo@redhat.com>
* config/mips/linux.h: Add #undef for SUBTARGET_CPP_SPEC.
* config/mips/mips.h: Remove deprecated -m<processor> options
and cc1_cpu_spec associated.
(CONSTANT_ADDRESS_P): Fix last patch.
(ASM_DECLARE_FUNCTION_NAME): Declare. Fix comment.
* config/mips/mips.md (bungt, bunge, sungt_df, sungt_sf, sunge_df,
sunge_sf): Remove.
2002-07-03 Stan Shebs <shebs@apple.com>
* config/darwin.h (APPLE_CC): Remove, not meaningful in FSF GCC.

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@ -171,6 +171,7 @@ void FN () \
builtin_define ("_MIPS_SZINT=32"); \
} while (0)
#undef SUBTARGET_CPP_SPEC
#define SUBTARGET_CPP_SPEC "\
%{fno-PIC:-U__PIC__ -U__pic__} %{fno-pic:-U__PIC__ -U__pic__} \
%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} \

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@ -561,10 +561,6 @@ extern void sbss_section PARAMS ((void));
N_("Work around early 4300 hardware bug")}, \
{"no-fix4300", -MASK_4300_MUL_FIX, \
N_("Don't work around early 4300 hardware bug")}, \
{"3900", 0, \
N_("Optimize for 3900")}, \
{"4650", 0, \
N_("Optimize for 4650")}, \
{"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
N_("Trap on integer divide by zero")}, \
{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
@ -1044,16 +1040,6 @@ extern int mips_abi;
#define SUBTARGET_CC1_SPEC ""
#endif
/* Deal with historic options. */
#ifndef CC1_CPU_SPEC
#define CC1_CPU_SPEC "\
%{!mcpu*: \
%{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
%n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
%{m4650:-march=r4650 -mmad -msingle-float \
%n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
#endif
/* CC1_SPEC is the set of arguments to pass to the compiler proper. */
/* Note, we will need to adjust the following if we ever find a MIPS variant
that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
@ -1073,8 +1059,7 @@ extern int mips_abi;
%{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
%{save-temps: } \
%(subtarget_cc1_spec) \
%(cc1_cpu_spec)"
%(subtarget_cc1_spec)"
#endif
/* Preprocessor specs. */
@ -1099,7 +1084,6 @@ extern int mips_abi;
#define EXTRA_SPECS \
{ "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
{ "cc1_cpu_spec", CC1_CPU_SPEC}, \
{ "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
{ "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
{ "gas_asm_spec", GAS_ASM_SPEC }, \
@ -2989,9 +2973,10 @@ typedef struct mips_args {
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST \
&& ! (flag_pic && pic_address_needs_scratch (X)) \
&& (!TARGET_GAS) \
&& (mips_abi == ABI_N32 \
|| mips_abi == ABI_64)))
&& (TARGET_GAS) \
&& (mips_abi != ABI_N32 \
&& mips_abi != ABI_64)))
/* Define this, so that when PIC, reload won't try to reload invalid
addresses which require two reload registers. */
@ -4275,11 +4260,12 @@ do { \
/* This is how to declare a function name. The actual work of
emitting the label is moved to function_prologue, so that we can
get the line number correctly emitted before the .ent directive,
and after any .file directives. */
/*
and after any .file directives. Define to NULL so that the function
is not declared before the .ent directive elsewhere. */
#undef ASM_DECLARE_FUNCTION_NAME
#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
*/
/* This is how to output an internal numbered label where
PREFIX is the class of label and NUM is the number within the class. */

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@ -8095,22 +8095,6 @@ move\\t%0,%z4\\n\\
}
}")
(define_expand "bungt"
[(set (pc)
(if_then_else (ungt:CC (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
""
"
{
if (operands[0]) /* avoid unused code warning */
{
gen_conditional_branch (operands, UNGT);
DONE;
}
}")
(define_expand "bunlt"
[(set (pc)
(if_then_else (unlt:CC (cc0)
@ -8143,22 +8127,6 @@ move\\t%0,%z4\\n\\
}
}")
(define_expand "bunge"
[(set (pc)
(if_then_else (unge:CC (cc0)
(const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
""
"
{
if (operands[0]) /* avoid unused code warning */
{
gen_conditional_branch (operands, UNGE);
DONE;
}
}")
(define_expand "bunle"
[(set (pc)
(if_then_else (unle:CC (cc0)
@ -9255,18 +9223,6 @@ move\\t%0,%z4\\n\\
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sungt_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(ungt:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"*
{
return mips_fill_delay_slot (\"c.ugt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunlt_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(unlt:CC (match_operand:DF 1 "register_operand" "f")
@ -9291,18 +9247,6 @@ move\\t%0,%z4\\n\\
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunge_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(unge:CC (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"*
{
return mips_fill_delay_slot (\"c.uge.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunle_df"
[(set (match_operand:CC 0 "register_operand" "=z")
(unle:CC (match_operand:DF 1 "register_operand" "f")
@ -9399,18 +9343,6 @@ move\\t%0,%z4\\n\\
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sungt_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(ungt:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"*
{
return mips_fill_delay_slot (\"c.ugt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunlt_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(unlt:CC (match_operand:SF 1 "register_operand" "f")
@ -9435,18 +9367,6 @@ move\\t%0,%z4\\n\\
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunge_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(unge:CC (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"*
{
return mips_fill_delay_slot (\"c.uge.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
}"
[(set_attr "type" "fcmp")
(set_attr "mode" "FPSW")])
(define_insn "sunle_sf"
[(set (match_operand:CC 0 "register_operand" "=z")
(unle:CC (match_operand:SF 1 "register_operand" "f")