constraints.md (wo constraint): New constraint for ISA 3.0 (power9).
[gcc] 2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/constraints.md (wo constraint): New constraint for ISA 3.0 (power9). * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add support for wo constraint. (rs6000_init_hard_regno_mode_ok): Likewise. * config/rs6000/rs6000.h (r6000_reg_class_enum): Add support for wo constraint. * config/rs6000/altivec.md (altivec_vperm_<mode>): Clean up vperm expanders not to have constraints. Add support for ISA 3.0 xxperm instruction. Add support for fusing xxlor with xxperm. (altivec_vperm_<mode>_internal): Likewise. (altivec_vperm_v8hiv16qi): Likewise. (altivec_vperm_<mode>v16q): Likewise. (altivec_vperm_<mode>_uns): Likewise. (vperm_v8hiv4si): Likewise. (vperm_v16qiv8hi): Likewise. * doc/md.texi (RS/6000 constraints): Document wo constraint. [gcc/testsuite] 2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com> * gcc.target/powerpc/p9-permute.c: New test for xxperm code generation. From-SVN: r232060
This commit is contained in:
Michael Meissner
Michael Meissner
parent
f29fa917a5
commit
4e8a3a35d8
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@ -1,3 +1,27 @@
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2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/constraints.md (wo constraint): New constraint for
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ISA 3.0 (power9).
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* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add support
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for wo constraint.
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(rs6000_init_hard_regno_mode_ok): Likewise.
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* config/rs6000/rs6000.h (r6000_reg_class_enum): Add support for
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wo constraint.
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* config/rs6000/altivec.md (altivec_vperm_<mode>): Clean up vperm
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expanders not to have constraints. Add support for ISA 3.0 xxperm
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instruction. Add support for fusing xxlor with xxperm.
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(altivec_vperm_<mode>_internal): Likewise.
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(altivec_vperm_v8hiv16qi): Likewise.
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(altivec_vperm_<mode>v16q): Likewise.
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(altivec_vperm_<mode>_uns): Likewise.
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(vperm_v8hiv4si): Likewise.
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(vperm_v16qiv8hi): Likewise.
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* doc/md.texi (RS/6000 constraints): Document wo constraint.
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2016-01-04 Jakub Jelinek <jakub@redhat.com>
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Update copyright years.
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@ -1933,10 +1933,10 @@
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[(set_attr "type" "vecfloat")])
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(define_expand "altivec_vperm_<mode>"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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[(set (match_operand:VM 0 "register_operand" "")
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(unspec:VM [(match_operand:VM 1 "register_operand" "")
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(match_operand:VM 2 "register_operand" "")
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(match_operand:V16QI 3 "register_operand" "")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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{
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@ -1947,31 +1947,40 @@
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}
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})
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;; Slightly prefer vperm, since the target does not overlap the source
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(define_insn "*altivec_vperm_<mode>_internal"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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[(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo")
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(match_operand:VM 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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"vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")])
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(define_insn "altivec_vperm_v8hiv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
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(match_operand:V8HI 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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[(set (match_operand:V16QI 0 "register_operand" "=v,?wo,?&wo")
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(unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v,0,wo")
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(match_operand:V8HI 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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"vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")])
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(define_expand "altivec_vperm_<mode>_uns"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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[(set (match_operand:VM 0 "register_operand" "")
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(unspec:VM [(match_operand:VM 1 "register_operand" "")
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(match_operand:VM 2 "register_operand" "")
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(match_operand:V16QI 3 "register_operand" "")]
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UNSPEC_VPERM_UNS))]
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"TARGET_ALTIVEC"
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{
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@ -1983,14 +1992,18 @@
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})
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(define_insn "*altivec_vperm_<mode>_uns_internal"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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[(set (match_operand:VM 0 "register_operand" "=v,?wo,?&wo")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v,0,wo")
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(match_operand:VM 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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UNSPEC_VPERM_UNS))]
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"TARGET_ALTIVEC"
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"vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")])
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(define_expand "vec_permv16qi"
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[(set (match_operand:V16QI 0 "register_operand" "")
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@ -2778,24 +2791,32 @@
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"")
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(define_insn "vperm_v8hiv4si"
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[(set (match_operand:V4SI 0 "register_operand" "=v")
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(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
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(match_operand:V4SI 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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[(set (match_operand:V4SI 0 "register_operand" "=v,?wo,?&wo")
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(unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v,0,wo")
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(match_operand:V4SI 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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UNSPEC_VPERMSI))]
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"TARGET_ALTIVEC"
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"vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")])
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(define_insn "vperm_v16qiv8hi"
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[(set (match_operand:V8HI 0 "register_operand" "=v")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
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(match_operand:V8HI 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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[(set (match_operand:V8HI 0 "register_operand" "=v,?wo,?&wo")
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(unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v,0,wo")
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(match_operand:V8HI 2 "register_operand" "v,wo,wo")
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(match_operand:V16QI 3 "register_operand" "v,wo,wo")]
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UNSPEC_VPERMHI))]
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"TARGET_ALTIVEC"
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"vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")])
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"@
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vperm %0,%1,%2,%3
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xxperm %x0,%x2,%x3
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xxlor %x0,%x1,%x1\t\t# xxperm fusion\;xxperm %x0,%x2,%x3"
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[(set_attr "type" "vecperm")
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(set_attr "length" "4,4,8")])
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(define_expand "vec_unpacku_hi_v16qi"
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@ -99,7 +99,8 @@
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;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode
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(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).")
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;; wo is not currently used
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(define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]"
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"VSX register if the -mpower9-vector option was used or NO_REGS.")
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(define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]"
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"VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.")
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@ -2284,6 +2284,7 @@ rs6000_debug_reg_global (void)
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"wk reg_class = %s\n"
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"wl reg_class = %s\n"
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"wm reg_class = %s\n"
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"wo reg_class = %s\n"
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"wp reg_class = %s\n"
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"wq reg_class = %s\n"
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"wr reg_class = %s\n"
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@ -2311,6 +2312,7 @@ rs6000_debug_reg_global (void)
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
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reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
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@ -3019,7 +3021,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
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if (TARGET_P9_DFORM)
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rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
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/* Support for new direct moves. */
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/* Support for ISA 3.0 (power9) vectors. */
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if (TARGET_P9_VECTOR)
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rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
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/* Support for new direct moves (ISA 3.0 + 64bit). */
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if (TARGET_DIRECT_MOVE_128)
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rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
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@ -1535,6 +1535,7 @@ enum r6000_reg_class_enum {
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RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
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RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
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RS6000_CONSTRAINT_wm, /* VSX register for direct move */
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RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */
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RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
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RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
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RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
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@ -3102,8 +3102,8 @@ Any VSX register if the -mvsx option was used or NO_REGS.
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When using any of the register constraints (@code{wa}, @code{wd},
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@code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
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@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt},
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@code{wu}, @code{wv}, @code{ww}, or @code{wy})
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@code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws},
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@code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy})
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that take VSX registers, you must use @code{%x<n>} in the template so
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that the correct register is used. Otherwise the register number
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output in the assembly file will be incorrect if an Altivec register
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@ -3175,6 +3175,9 @@ VSX register if direct move instructions are enabled, or NO_REGS.
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@item wn
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No register (NO_REGS).
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@item wo
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VSX register to use for ISA 3.0 vector instructions, or NO_REGS.
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@item wp
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VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS.
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@ -1,3 +1,8 @@
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2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
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* gcc.target/powerpc/p9-permute.c: New test for xxperm code
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generation.
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2016-01-04 Jakub Jelinek <jakub@redhat.com>
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Update copyright years.
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@ -0,0 +1,20 @@
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/* { dg-do compile { target { powerpc64le-*-* } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-options "-mcpu=power9 -O2" } */
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#include <altivec.h>
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vector long long
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permute (vector long long *p, vector long long *q, vector unsigned char mask)
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{
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vector long long a = *p;
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vector long long b = *q;
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/* Force a, b to be in FPR registers. */
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__asm__ (" # a: %x0, b: %x1" : "+d" (a), "+d" (b));
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return vec_perm (a, b, mask);
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}
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/* { dg-final { scan-assembler "xxperm" } } */
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/* { dg-final { scan-assembler-not "vperm" } } */
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