Fix missing initializer compile-time warning messages.
* a29k/a29k.h (TARGET_SWITCHES): Add doc strings. * i960/i960.h (TARGET_SWITCHES): Add doc strings. * invoke.texi (a29k): Add documentation for -mno-multm option. From-SVN: r25981
This commit is contained in:
Jim Wilson
Jim Wilson
parent
5fa671cf5b
commit
4e8d7ddc2a
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@ -1,3 +1,9 @@
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Thu Mar 25 12:46:37 1999 Jim Wilson <wilson@cygnus.com>
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* a29k/a29k.h (TARGET_SWITCHES): Add doc strings.
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* i960/i960.h (TARGET_SWITCHES): Add doc strings.
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* invoke.texi (a29k): Add documentation for -mno-multm option.
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Thu Mar 25 14:04:54 EST 1999 Andrew MacLeod <amacleod@cygnus.com>
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* rtl.texi (RTX_FRAME_RELATED_P): Add documentation.
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@ -97,26 +97,26 @@ extern int target_flags;
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#define TARGET_MULTM ((target_flags & 1024) == 0)
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#define TARGET_SWITCHES \
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{ {"dw", 1}, \
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{"ndw", -1}, \
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{"bw", 2}, \
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{"nbw", - (1|2)}, \
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{"small", 4}, \
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{"normal", - (4|8)}, \
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{"large", 8}, \
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{"29050", 16+128}, \
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{"29000", -16}, \
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{"kernel-registers", 32}, \
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{"user-registers", -32}, \
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{"stack-check", 64}, \
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{"no-stack-check", - 74}, \
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{"storem-bug", -128}, \
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{"no-storem-bug", 128}, \
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{"reuse-arg-regs", -256}, \
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{"no-reuse-arg-regs", 256}, \
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{"soft-float", 512}, \
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{"no-multm", 1024}, \
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{"", TARGET_DEFAULT}}
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{ {"dw", 1, "Generate code assuming DW bit is set"}, \
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{"ndw", -1, "Generate code assuming DW bit is not set"}, \
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{"bw", 2, "Generate code using byte writes"}, \
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{"nbw", - (1|2), "Do not generate byte writes"}, \
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{"small", 4, "Use small memory model"}, \
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{"normal", - (4|8), "Use normal memory model"}, \
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{"large", 8, "Use large memory model"}, \
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{"29050", 16+128, "Generate 29050 code"}, \
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{"29000", -16, "Generate 29000 code"}, \
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{"kernel-registers", 32, "Use kernel global registers"}, \
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{"user-registers", -32, "Use user global registers"}, \
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{"stack-check", 64, "Emit stack checking code"}, \
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{"no-stack-check", - 74, "Do not emit stack checking code"}, \
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{"storem-bug", -128, "Work around storem hardware bug"}, \
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{"no-storem-bug", 128, "Do not work around storem hardware bug"}, \
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{"reuse-arg-regs", -256, "Store locals in argument registers"}, \
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{"no-reuse-arg-regs", 256, "Do not store locals in arg registers"}, \
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{"soft-float", 512, "Use software floating point"}, \
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{"no-multm", 1024, "Do not generate multm instructions"}, \
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{"", TARGET_DEFAULT, NULL}}
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#define TARGET_DEFAULT 3
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@ -229,58 +229,98 @@ extern int target_flags;
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am not sure which are real and which aren't. */
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#define TARGET_SWITCHES \
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{ {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
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{"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
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TARGET_FLAG_COMPLEX_ADDR)},\
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/* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
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TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
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{"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
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{"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
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TARGET_FLAG_COMPLEX_ADDR)},\
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/* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
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TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
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{"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
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{"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
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{"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
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TARGET_FLAG_COMPLEX_ADDR)},\
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{"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
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{"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
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TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
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{"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
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TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
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/* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
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TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
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{"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
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{ {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
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"Generate SA code"}, \
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{"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
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TARGET_FLAG_COMPLEX_ADDR), \
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"Generate SB code"}, \
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/* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
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TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
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"Generate SC code"}, */ \
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{"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
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"Generate KA code"}, \
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{"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
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TARGET_FLAG_COMPLEX_ADDR), \
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"Generate KB code"}, \
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/* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
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TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
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"Generate KC code"}, */ \
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{"ja", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
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"Generate JA code"}, \
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{"jd", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
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"Generate JD code"}, \
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{"jf", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
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TARGET_FLAG_COMPLEX_ADDR), \
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"Generate JF code"}, \
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{"rp", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR), \
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"generate RP code"}, \
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{"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
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TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR), \
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"Generate MC code"}, \
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{"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
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TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
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"Generate CA code"}, \
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/* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES| \
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TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN),\
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"Generate CB code"}, \
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{"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED| \
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TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
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TARGET_FLAG_CODE_ALIGN)}, */ \
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{"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
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TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
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{"numerics", (TARGET_FLAG_NUMERICS)}, \
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{"soft-float", -(TARGET_FLAG_NUMERICS)}, \
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{"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
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{"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
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{"tail-call",TARGET_FLAG_TAILCALL}, \
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{"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
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{"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
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{"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
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{"code-align",TARGET_FLAG_CODE_ALIGN}, \
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{"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
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{"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
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{"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
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{"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
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{"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
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{"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
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{"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
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{"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
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{"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
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{"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
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{"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
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{"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
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{"long-double-64", TARGET_FLAG_LONG_DOUBLE_64}, \
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{"link-relax", 0}, \
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{"no-link-relax", 0}, \
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TARGET_FLAG_CODE_ALIGN), \
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"Generate CC code"}, */ \
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{"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT| \
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TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR),\
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"Generate CF code"}, \
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{"numerics", (TARGET_FLAG_NUMERICS), \
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"Use hardware floating point instructions"}, \
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{"soft-float", -(TARGET_FLAG_NUMERICS), \
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"Use software floating point"}, \
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{"leaf-procedures", TARGET_FLAG_LEAFPROC, \
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"Use alternate leaf function entries"}, \
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{"no-leaf-procedures", -(TARGET_FLAG_LEAFPROC), \
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"Do not use alternate leaf function entries"}, \
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{"tail-call", TARGET_FLAG_TAILCALL, \
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"Perform tail call optimization"}, \
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{"no-tail-call", -(TARGET_FLAG_TAILCALL), \
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"Do not perform tail call optimization"}, \
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{"complex-addr", TARGET_FLAG_COMPLEX_ADDR, \
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"Use complex addressing modes"}, \
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{"no-complex-addr", -(TARGET_FLAG_COMPLEX_ADDR), \
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"Do not use complex addressing modes"}, \
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{"code-align", TARGET_FLAG_CODE_ALIGN, \
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"Align code to 8 byte boundary"}, \
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{"no-code-align", -(TARGET_FLAG_CODE_ALIGN), \
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"Do not align code to 8 byte boundary"}, \
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/* {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE), \
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"Force use of prototypes"}, \
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{"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE), \
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"Do not force use of prototypes"}, */ \
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{"ic-compat", TARGET_FLAG_IC_COMPAT2_0, \
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"Enable compatibility with iC960 v2.0"}, \
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{"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0, \
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"Enable compatibility with iC960 v2.0"}, \
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{"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0, \
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"Enable compatibility with iC960 v3.0"}, \
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{"asm-compat", TARGET_FLAG_ASM_COMPAT, \
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"Enable compatibility with ic960 assembler"}, \
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{"intel-asm", TARGET_FLAG_ASM_COMPAT, \
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"Enable compatibility with ic960 assembler"}, \
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{"strict-align", TARGET_FLAG_STRICT_ALIGN, \
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"Do not permit unaligned accesses"}, \
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{"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN), \
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"Permit unaligned accesses"}, \
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{"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
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"Layout types like Intel's v1.3 gcc"}, \
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{"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN), \
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"Do not layout types like Intel's v1.3 gcc"}, \
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{"long-double-64", TARGET_FLAG_LONG_DOUBLE_64, \
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"Use 64 bit long doubles"}, \
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{"link-relax", 0, \
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"Enable linker relaxation"}, \
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{"no-link-relax", 0, \
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"Do not enable linker relaxation"}, \
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SUBTARGET_SWITCHES \
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{ "", TARGET_DEFAULT}}
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{ "", TARGET_DEFAULT, \
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NULL}}
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/* This are meant to be redefined in the host dependent files */
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#define SUBTARGET_SWITCHES
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@ -3644,6 +3644,11 @@ Normally the facilities of the machine's usual C compiler are used, but
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this can't be done directly in cross-compilation. You must make your
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own arrangements to provide suitable library functions for
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cross-compilation.
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@item -mno-multm
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@kindex -mno-multm
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Do not generate multm or multmu instructions. This is useful for some embedded
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systems which do not have trap handlers for these instructions.
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@end table
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@node ARM Options
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