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[AArch64 1/3] Don't disparage add/sub in SIMD registers

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* config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize 
        SIMD reg variant.

From-SVN: r218958
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Alan Lawrence 2014-12-19 17:44:36 +00:00 committed by Alan Lawrence
parent fc2770b996
commit 4f2962fd47
2 changed files with 11 additions and 6 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2014-12-19 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize
SIMD reg variant.
2014-12-19 Martin Liska <mliska@suse.cz>
PR ipa/63569

12
gcc/config/aarch64/aarch64.md
View File

@ -1434,10 +1434,10 @@
(define_insn "*adddi3_aarch64"
[(set
(match_operand:DI 0 "register_operand" "=rk,rk,rk,!w")
(match_operand:DI 0 "register_operand" "=rk,rk,rk,w")
(plus:DI
(match_operand:DI 1 "register_operand" "%rk,rk,rk,!w")
(match_operand:DI 2 "aarch64_plus_operand" "I,r,J,!w")))]
(match_operand:DI 1 "register_operand" "%rk,rk,rk,w")
(match_operand:DI 2 "aarch64_plus_operand" "I,r,J,w")))]
""
"@
add\\t%x0, %x1, %2
@ -1908,9 +1908,9 @@
)
(define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=rk,!w")
(minus:DI (match_operand:DI 1 "register_operand" "r,!w")
(match_operand:DI 2 "register_operand" "r,!w")))]
[(set (match_operand:DI 0 "register_operand" "=rk,w")
(minus:DI (match_operand:DI 1 "register_operand" "r,w")
(match_operand:DI 2 "register_operand" "r,w")))]
""
"@
sub\\t%x0, %x1, %x2