RISC-V: Short-forward-branch opt for SiFive 7 series cores.
gcc/ * config/riscv/constraints.md (L): New. * config/riscv/predicates.md (lui_operand): New. (sfb_alu_operand): New. * config/riscv/riscv-protos.h (riscv_expand_conditional_move): Declare. * config/riscv/riscv.c (riscv_expand_conditional_move): New. * config/riscv/riscv.h (TARGET_SFB_ALU): New. * config/riscv/risc.md (type): Add sfb_alu. (branch<mode>): Renamed from branch_order<mode>. Change predicate for operand 3 to reg_or_0_operand. In output string, change %3 to %z3. (branch_zero<mode>): Delete. (mov<mode>cc): New. (mov<GPR:mode><X:mode>cc): Likewise. * config/riscv/sifive-7.md (sifive_7_sfb_alu): New. Use in bypasses. From-SVN: r270758
This commit is contained in:
Andrew Waterman
Jim Wilson
parent
598f50d789
commit
4f47539144
@ -1,3 +1,19 @@
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2019-04-30 Jim Wilson <jimw@sifive.com>
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* config/riscv/constraints.md (L): New.
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* config/riscv/predicates.md (lui_operand): New.
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(sfb_alu_operand): New.
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* config/riscv/riscv-protos.h (riscv_expand_conditional_move): Declare.
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* config/riscv/riscv.c (riscv_expand_conditional_move): New.
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* config/riscv/riscv.h (TARGET_SFB_ALU): New.
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* config/riscv/risc.md (type): Add sfb_alu.
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(branch<mode>): Renamed from branch_order<mode>. Change predicate for
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operand 3 to reg_or_0_operand. In output string, change %3 to %z3.
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(branch_zero<mode>): Delete.
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(mov<mode>cc): New.
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(mov<GPR:mode><X:mode>cc): Likewise.
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* config/riscv/sifive-7.md (sifive_7_sfb_alu): New. Use in bypasses.
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2019-04-30 Nathan Sidwell <nathan@acm.org>
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* tree.h (MARK_TS_EXP): New.
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@ -49,6 +49,11 @@
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(and (match_code "const_int")
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(match_test "IN_RANGE (ival, 0, 31)")))
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(define_constraint "L"
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"A U-type 20-bit signed immediate."
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(and (match_code "const_int")
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(match_test "LUI_OPERAND (ival)")))
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;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
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;; not available in RV32.
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(define_constraint "G"
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@ -27,6 +27,14 @@
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(ior (match_operand 0 "const_arith_operand")
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(match_operand 0 "register_operand")))
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(define_predicate "lui_operand"
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(and (match_code "const_int")
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(match_test "LUI_OPERAND (INTVAL (op))")))
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(define_predicate "sfb_alu_operand"
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(ior (match_operand 0 "arith_operand")
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(match_operand 0 "lui_operand")))
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(define_predicate "const_csr_operand"
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(and (match_code "const_int")
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(match_test "IN_RANGE (INTVAL (op), 0, 31)")))
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@ -59,6 +59,7 @@ extern const char *riscv_output_return ();
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extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx);
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extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
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extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
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extern void riscv_expand_conditional_move (rtx, rtx, rtx, rtx_code, rtx, rtx);
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#endif
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extern rtx riscv_legitimize_call_address (rtx);
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extern void riscv_set_return_address (rtx, rtx);
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@ -2324,6 +2324,18 @@ riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1)
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emit_jump_insn (gen_condjump (condition, label));
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}
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/* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */
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void
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riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code,
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rtx op0, rtx op1)
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{
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riscv_emit_int_compare (&code, &op0, &op1);
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rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
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emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond,
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cons, alt)));
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}
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/* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
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least PARM_BOUNDARY bits of alignment, but will be given anything up
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to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
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@ -662,6 +662,17 @@ typedef struct {
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#define BRANCH_COST(speed_p, predictable_p) \
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((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
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/* True if the target optimizes short forward branches around integer
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arithmetic instructions into predicated operations, e.g., for
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conditional-move operations. The macro assumes that all branch
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instructions (BEQ, BNE, BLT, BLTU, BGE, BGEU, C.BEQZ, and C.BNEZ)
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support this feature. The macro further assumes that any integer
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arithmetic and logical operation (ADD[I], SUB, SLL[I], SRL[I], SRA[I],
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SLT[I][U], AND[I], XOR[I], OR[I], LUI, AUIPC, and their compressed
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counterparts, including C.MV and C.LI) can be in the branch shadow. */
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#define TARGET_SFB_ALU (riscv_microarchitecture == sifive_7)
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#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
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/* Control the assembler format that we output. */
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@ -156,7 +156,7 @@
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(define_attr "type"
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"unknown,branch,jump,call,load,fpload,store,fpstore,
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mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
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fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,nop,ghost"
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fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost"
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(cond [(eq_attr "got" "load") (const_string "load")
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;; If a doubleword move uses these expensive instructions,
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@ -1804,31 +1804,52 @@
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;; Conditional branches
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(define_insn "*branch_order<mode>"
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(define_insn "*branch<mode>"
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[(set (pc)
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(if_then_else
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(match_operator 1 "order_operator"
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[(match_operand:X 2 "register_operand" "r")
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(match_operand:X 3 "register_operand" "r")])
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(match_operand:X 3 "reg_or_0_operand" "rJ")])
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"b%C1\t%2,%3,%0"
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"b%C1\t%2,%z3,%0"
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[(set_attr "type" "branch")
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(set_attr "mode" "none")])
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(define_insn "*branch_zero<mode>"
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[(set (pc)
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(if_then_else
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(match_operator 1 "signed_order_operator"
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[(match_operand:X 2 "register_operand" "r")
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(const_int 0)])
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(label_ref (match_operand 0 "" ""))
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(pc)))]
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""
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"b%C1z\t%2,%0"
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[(set_attr "type" "branch")
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(set_attr "mode" "none")])
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;; Patterns for implementations that optimize short forward branches.
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(define_expand "mov<mode>cc"
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[(set (match_operand:GPR 0 "register_operand")
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(if_then_else:GPR (match_operand 1 "comparison_operator")
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(match_operand:GPR 2 "register_operand")
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(match_operand:GPR 3 "sfb_alu_operand")))]
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"TARGET_SFB_ALU"
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{
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rtx cmp = operands[1];
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/* We only handle word mode integer compares for now. */
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if (GET_MODE (XEXP (cmp, 0)) != word_mode)
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FAIL;
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riscv_expand_conditional_move (operands[0], operands[2], operands[3],
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GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1));
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DONE;
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})
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(define_insn "*mov<GPR:mode><X:mode>cc"
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[(set (match_operand:GPR 0 "register_operand" "=r,r")
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(if_then_else:GPR
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(match_operator 5 "order_operator"
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[(match_operand:X 1 "register_operand" "r,r")
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(match_operand:X 2 "reg_or_0_operand" "rJ,rJ")])
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(match_operand:GPR 3 "register_operand" "0,0")
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(match_operand:GPR 4 "sfb_alu_operand" "rJ,IL")))]
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"TARGET_SFB_ALU"
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"@
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b%C5 %1,%z2,1f; mv %0,%z4; 1: # movcc
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b%C5 %1,%z2,1f; li %0,%4; 1: # movcc"
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[(set_attr "length" "8")
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(set_attr "type" "sfb_alu")
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(set_attr "mode" "<GPR:MODE>")])
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;; Used to implement built-in functions.
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(define_expand "condjump"
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@ -37,6 +37,11 @@
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(eq_attr "type" "branch"))
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"sifive_7_B")
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(define_insn_reservation "sifive_7_sfb_alu" 2
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(and (eq_attr "tune" "sifive_7")
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(eq_attr "type" "sfb_alu"))
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"sifive_7_A+sifive_7_B")
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(define_insn_reservation "sifive_7_jump" 1
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(and (eq_attr "tune" "sifive_7")
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(eq_attr "type" "jump,call"))
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@ -101,10 +106,13 @@
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(eq_attr "type" "mfc"))
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"sifive_7_A")
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(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i"
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(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
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"sifive_7_alu,sifive_7_branch")
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(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i"
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(define_bypass 1 "sifive_7_alu,sifive_7_sfb_alu"
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"sifive_7_sfb_alu")
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(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
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"sifive_7_store" "riscv_store_data_bypass_p")
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(define_bypass 2 "sifive_7_i2f"
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