2012-10-30 James Greenhalgh <james.greenhalgh@arm.com>
Tejas Belagod <tejas.belagod@arm.com> * config/aarch64/aarch64-simd.md (aarch64_simd_bsl<mode>_internal): New pattern. (aarch64_simd_bsl<mode>): Likewise. (aarch64_vcond_internal<mode>): Likewise. (vcondu<mode><mode>): Likewise. (vcond<mode><mode>): Likewise. * config/aarch64/iterators.md (UNSPEC_BSL): Add to define_constants. Co-Authored-By: Tejas Belagod <tejas.belagod@arm.com> From-SVN: r192985
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James Greenhalgh
James Greenhalgh
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@ -1,3 +1,14 @@
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2012-10-30 James Greenhalgh <james.greenhalgh@arm.com>
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Tejas Belagod <tejas.belagod@arm.com>
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* config/aarch64/aarch64-simd.md
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(aarch64_simd_bsl<mode>_internal): New pattern.
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(aarch64_simd_bsl<mode>): Likewise.
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(aarch64_vcond_internal<mode>): Likewise.
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(vcondu<mode><mode>): Likewise.
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(vcond<mode><mode>): Likewise.
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* config/aarch64/iterators.md (UNSPEC_BSL): Add to define_constants.
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2012-10-30 Richard Biener <rguenther@suse.de>
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2012-10-30 Richard Biener <rguenther@suse.de>
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PR tree-optimization/55111
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PR tree-optimization/55111
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@ -1467,6 +1467,150 @@
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(set_attr "simd_mode" "V2SI")]
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(set_attr "simd_mode" "V2SI")]
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)
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)
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;; vbsl_* intrinsics may compile to any of vbsl/vbif/vbit depending on register
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;; allocation. For an intrinsic of form:
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;; vD = bsl_* (vS, vN, vM)
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;; We can use any of:
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;; bsl vS, vN, vM (if D = S)
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;; bit vD, vN, vS (if D = M, so 1-bits in vS choose bits from vN, else vM)
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;; bif vD, vM, vS (if D = N, so 0-bits in vS choose bits from vM, else vN)
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(define_insn "aarch64_simd_bsl<mode>_internal"
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[(set (match_operand:VDQ 0 "register_operand" "=w,w,w")
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(unspec:VDQ [(match_operand:VDQ 1 "register_operand" " 0,w,w")
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(match_operand:VDQ 2 "register_operand" " w,w,0")
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(match_operand:VDQ 3 "register_operand" " w,0,w")]
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UNSPEC_BSL))]
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"TARGET_SIMD"
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"@
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bsl\\t%0.<Vbtype>, %2.<Vbtype>, %3.<Vbtype>
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bit\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>
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bif\\t%0.<Vbtype>, %3.<Vbtype>, %1.<Vbtype>"
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)
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(define_expand "aarch64_simd_bsl<mode>"
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[(set (match_operand:VDQ 0 "register_operand")
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(unspec:VDQ [(match_operand:<V_cmp_result> 1 "register_operand")
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(match_operand:VDQ 2 "register_operand")
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(match_operand:VDQ 3 "register_operand")]
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UNSPEC_BSL))]
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"TARGET_SIMD"
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{
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/* We can't alias operands together if they have different modes. */
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operands[1] = gen_lowpart (<MODE>mode, operands[1]);
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})
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(define_expand "aarch64_vcond_internal<mode>"
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[(set (match_operand:VDQ 0 "register_operand")
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(if_then_else:VDQ
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(match_operator 3 "comparison_operator"
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[(match_operand:VDQ 4 "register_operand")
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(match_operand:VDQ 5 "nonmemory_operand")])
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(match_operand:VDQ 1 "register_operand")
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(match_operand:VDQ 2 "register_operand")))]
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"TARGET_SIMD"
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{
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int inverse = 0, has_zero_imm_form = 0;
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rtx mask = gen_reg_rtx (<MODE>mode);
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switch (GET_CODE (operands[3]))
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{
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case LE:
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case LT:
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case NE:
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inverse = 1;
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/* Fall through. */
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case GE:
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case GT:
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case EQ:
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has_zero_imm_form = 1;
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break;
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case LEU:
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case LTU:
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inverse = 1;
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break;
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default:
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break;
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}
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if (!REG_P (operands[5])
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&& (operands[5] != CONST0_RTX (<MODE>mode) || !has_zero_imm_form))
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operands[5] = force_reg (<MODE>mode, operands[5]);
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switch (GET_CODE (operands[3]))
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{
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case LT:
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case GE:
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emit_insn (gen_aarch64_cmge<mode> (mask, operands[4], operands[5]));
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break;
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case LE:
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case GT:
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emit_insn (gen_aarch64_cmgt<mode> (mask, operands[4], operands[5]));
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break;
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case LTU:
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case GEU:
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emit_insn (gen_aarch64_cmhs<mode> (mask, operands[4], operands[5]));
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break;
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case LEU:
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case GTU:
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emit_insn (gen_aarch64_cmhi<mode> (mask, operands[4], operands[5]));
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break;
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case NE:
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case EQ:
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emit_insn (gen_aarch64_cmeq<mode> (mask, operands[4], operands[5]));
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break;
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default:
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gcc_unreachable ();
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}
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if (inverse)
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emit_insn (gen_aarch64_simd_bsl<mode> (operands[0], mask, operands[2],
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operands[1]));
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else
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emit_insn (gen_aarch64_simd_bsl<mode> (operands[0], mask, operands[1],
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operands[2]));
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DONE;
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})
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(define_expand "vcond<mode><mode>"
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[(set (match_operand:VDQ 0 "register_operand")
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(if_then_else:VDQ
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(match_operator 3 "comparison_operator"
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[(match_operand:VDQ 4 "register_operand")
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(match_operand:VDQ 5 "nonmemory_operand")])
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(match_operand:VDQ 1 "register_operand")
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(match_operand:VDQ 2 "register_operand")))]
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"TARGET_SIMD"
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{
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emit_insn (gen_aarch64_vcond_internal<mode> (operands[0], operands[1],
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operands[2], operands[3],
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operands[4], operands[5]));
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DONE;
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})
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(define_expand "vcondu<mode><mode>"
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[(set (match_operand:VDQ 0 "register_operand")
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(if_then_else:VDQ
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(match_operator 3 "comparison_operator"
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[(match_operand:VDQ 4 "register_operand")
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(match_operand:VDQ 5 "nonmemory_operand")])
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(match_operand:VDQ 1 "register_operand")
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(match_operand:VDQ 2 "register_operand")))]
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"TARGET_SIMD"
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{
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emit_insn (gen_aarch64_vcond_internal<mode> (operands[0], operands[1],
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operands[2], operands[3],
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operands[4], operands[5]));
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DONE;
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})
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;; Patterns for AArch64 SIMD Intrinsics.
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;; Patterns for AArch64 SIMD Intrinsics.
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(define_expand "aarch64_create<mode>"
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(define_expand "aarch64_create<mode>"
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@ -227,6 +227,7 @@
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UNSPEC_CMTST ; Used in aarch64-simd.md.
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UNSPEC_CMTST ; Used in aarch64-simd.md.
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UNSPEC_FMAX ; Used in aarch64-simd.md.
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UNSPEC_FMAX ; Used in aarch64-simd.md.
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UNSPEC_FMIN ; Used in aarch64-simd.md.
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UNSPEC_FMIN ; Used in aarch64-simd.md.
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UNSPEC_BSL ; Used in aarch64-simd.md.
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])
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])
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;; -------------------------------------------------------------------
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;; -------------------------------------------------------------------
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