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From-SVN: r8026
This commit is contained in:
Steve Chamberlain 1994-09-06 18:37:01 +00:00
parent 6922033c58
commit 4fdd1f85ce
3 changed files with 49 additions and 77 deletions
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33
gcc/config/sh/sh.c
View File

@ -127,19 +127,26 @@ void
push (rn)
int rn;
{
emit_insn (gen_push (gen_rtx (REG, SImode, rn)));
rtx x ;
x= emit_insn (gen_push (gen_rtx (REG, SImode, rn)));
REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
}
void
pop (rn)
int rn;
{
emit_insn (gen_pop (gen_rtx (REG, SImode, rn)));
rtx x;
x = emit_insn (gen_pop (gen_rtx (REG, SImode, rn)));
REG_NOTES (x) = gen_rtx (EXPR_LIST, REG_INC,
gen_rtx(REG, SImode, STACK_POINTER_REGNUM), 0);
}
/* Adjust the stack and return the number of bytes taken to do it */
static rtx lastreg;
int lastval;
static void
output_stack_adjust (size)
int size;
@ -151,9 +158,11 @@ output_stack_adjust (size)
if (!CONST_OK_FOR_I (size))
{
rtx nval = gen_rtx (REG, SImode, 3);
emit_insn (gen_movsi (nval, val));
val = nval;
lastreg = gen_rtx (REG, SImode, 3);
lastval = size;
emit_insn (gen_movsi (lastreg, val));
val = lastreg;
}
insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
@ -471,6 +480,7 @@ synth_constant (operands, mode)
dst = operands[0];
}
/* 00000000 00000000 11111111 1NNNNNNNN load and zero extend word */
if ((i & 0xffffff80) == 0x0000ff80)
{
@ -510,8 +520,8 @@ synth_constant (operands, mode)
}
/* 00000000 0NNNNNNN 00000000 000000000 load and shift by 16
11111111 1NNNNNNN 00000000 000000000 load and shift by 16 */
else if ((i & 0xff80ffff) == 0
|| (i & 0xff80ffff) == 0xff80ffff)
else if ((i & 0xff80ffff) == 0x00000000
|| (i & 0xff80ffff) == 0xff800000)
{
emit_move_insn (dst, GEN_INT (sextb (i >> 16)));
emit_insn (gen_ashlsi3_n (dst, dst, GEN_INT (16)));
@ -1046,9 +1056,11 @@ output_far_jump (insn, op)
break;
}
print_slot (final_sequence);
output_asm_insn ("mov.l %1,@-r15", vec);
output_asm_insn ("mov.l %O0,%1", vec);
print_slot (final_sequence);
output_asm_insn ("jmp @%1 ! 32 xcond", vec);
output_asm_insn ("mov.l @r15+,%1", vec);
}
@ -1365,7 +1377,7 @@ output_file_start (file, f_options, f_len, W_options, W_len)
data_section ();
pos = fprintf (file, "\n! Hitachi SH cc1 (%s) (release H-1) arguments:", version_string);
pos = fprintf (file, "\n! Hitachi SH cc1 (%s) (release I-1) arguments:", version_string);
output_options (file, f_options, f_len, W_options, W_len,
pos, 75, " ", "\n! ", "\n\n");
}
@ -2044,6 +2056,7 @@ sh_expand_epilogue ()
live_regs_mask = calc_live_regs (&d);
if (frame_pointer_needed)
{
emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));

2
gcc/config/sh/sh.h
View File

@ -800,7 +800,7 @@ extern int current_function_anonymous_args;
functions that have frame pointers.
No definition is equivalent to always zero. */
#define EXIT_IGNORE_STACK 0
#define EXIT_IGNORE_STACK 1
/* Generate the assembly code for function exit
Just dump out any accumulated constant table.*/

91
gcc/config/sh/sh.md
View File

@ -262,45 +262,17 @@
;; Addition instructions
;; -------------------------------------------------------------------------
;; this should be a define split.
(define_insn "addc"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(plus:SI (match_dup 0)
(plus:SI (match_operand:SI 1 "arith_reg_operand" "r")
(reg:SI 18))))
(define_insn "adddi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:SI 18))]
""
"addc %1,%0")
"clrt\;addc %R2,%R0\;addc %2,%0"
[(set_attr "length" "6")])
(define_expand "adddi3"
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))]
""
"
{
rtx low_a = operand_subword (operands[1], 1, 1, DImode);
rtx low_b = operand_subword (operands[2], 1, 1, DImode);
rtx low_s = operand_subword (operands[0], 1, 1, DImode);
rtx high_a = operand_subword (operands[1], 0, 1, DImode);
rtx high_b = operand_subword (operands[2], 0, 1, DImode);
rtx high_s = operand_subword (operands[0], 0, 1, DImode);
emit_insn (gen_clrt ());
emit_move_insn (low_s, low_a);
emit_insn (gen_addc (low_s, low_b));
emit_move_insn (high_s, high_a);
emit_insn (gen_addc (high_s, high_b));
DONE;
}")
(define_insn "addsi3_real"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
@ -324,36 +296,14 @@
;; -------------------------------------------------------------------------
(define_insn "subc"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
(minus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
(plus:SI (match_operand:SI 2 "arith_reg_operand" "r")
(reg:SI 18))))
(define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=r")
(minus:DI (match_operand:DI 1 "register_operand" "%0")
(match_operand:DI 2 "register_operand" "r")))
(clobber (reg:SI 18))]
""
"subc %2,%0")
(define_expand "subdi3"
[(set (match_operand:DI 0 "register_operand" "")
(plus:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")))]
""
"
{
rtx low_a = operand_subword (operands[1], 1, 1, DImode);
rtx low_b = operand_subword (operands[2], 1, 1, DImode);
rtx low_s = operand_subword (operands[0], 1, 1, DImode);
rtx high_a = operand_subword (operands[1], 0, 1, DImode);
rtx high_b = operand_subword (operands[2], 0, 1, DImode);
rtx high_s = operand_subword (operands[0], 0, 1, DImode);
emit_insn (gen_clrt ());
emit_insn (gen_subc (low_s, low_a, low_b));
emit_insn (gen_subc (high_s, high_a, high_b));
DONE;
}")
"clrt\;subc %R2,%R0\;subc %2,%0"
[(set_attr "length" "6")])
(define_insn "subsi3"
[(set (match_operand:SI 0 "arith_reg_operand" "=r")
@ -410,7 +360,8 @@
(div:SI (reg:SI 4) (reg:SI 5)))
(clobber (reg:SI 18))
(clobber (reg:SI 17))
(clobber (reg:SI 4))
(clobber (reg:SI 1))
(clobber (reg:SI 2))
(clobber (reg:SI 3))
(use (match_operand:SI 0 "register_operand" "r"))]
""
@ -428,7 +379,8 @@
(reg:SI 5)))
(clobber (reg:SI 18))
(clobber (reg:SI 17))
(clobber (reg:SI 4))
(clobber (reg:SI 1))
(clobber (reg:SI 2))
(clobber (reg:SI 3))
(use (match_dup 3))])
(set (match_operand:SI 0 "general_operand" "=g")
@ -1538,7 +1490,9 @@
(const_int 1))
(label_ref (match_operand 4 "" ""))
(pc)))
(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 5)))
(set (match_dup 6) (match_dup 5))
(parallel[(set (match_dup 6) (ashift:SI (match_dup 6) (match_dup 7)))
(clobber (reg:SI 18))])
(set (reg:SI 0) (label_ref (match_operand 3 "" "")))
(parallel[(set (reg:SI 0) (plus:SI (reg:SI 0)
(mem:HI (plus:SI (reg:SI 0)
@ -1552,6 +1506,7 @@
operands[2] = copy_to_mode_reg (SImode, operands[2]);
operands[5] = gen_reg_rtx (SImode);
operands[6] = gen_reg_rtx (SImode);
operands[7] = GEN_INT (TARGET_BIGTABLE ? 2 : 1);
}")
(define_insn "casesi_worker"
@ -1562,7 +1517,11 @@
(set (match_dup 0) (mem:HI (plus:SI (reg:SI 0)
(match_dup 0))))]
""
"mov.w @(r0,%0),%0\;add %0,r0"
"*
if (TARGET_BIGTABLE)
return \"mov.l @(r0,%0),%0\;add %0,r0\";
else
return \"mov.w @(r0,%0),%0\;add %0,r0\";"
[(set_attr "needs_delay_slot" "no")
(set_attr "in_delay_slot" "no")
(set_attr "length" "4")])