rs6000.md (maxsf3): Use rs6000_emit_minmax.
* config/rs6000/rs6000.md (maxsf3): Use rs6000_emit_minmax. (maxsf3+1): Delete. (minsf3): Use rs6000_emit_minmax. (minsf3+1): Generalize to handle both SMIN and SMAX. Use rs6000_emit_minmax. (movsfcc): Use rs6000_emit_cmove. (fselsfsf4): Don't compare a CONST_INT with a floating-point value. Don't generate emit_fselsfsf4. (fseldfsf4): Likewise. (maxdf3): Use rs6000_emit_minmax. (maxdf3+1): Delete. (mindf3): Use rs6000_emit_minmax. (mindf3+1): Generalize to handle both SMIN and SMAX. Use rs6000_emit_minmax. (movdfcc): Use rs6000_emit_cmove. (fseldfdf4): Don't compare a CONST_INT with a floating-point value. Don't generate emit_fselsfsf4. (fselsfdf4): Likewise. * config/rs6000/rs6000.c (zero_fp_constant): New predicate. (min_max_operator): New predicate. (rs6000_emit_cmove): New function. (rs6000_emit_minmax): New function. * config/rs6000/rs6000-protos.h: Prototype new functions. * config/rs6000/rs6000.h (PREDICATE_CODES): Add zero_fp_constant and min_max_operator. * config/rs6000/rs6000.c (output_cbranch): Handle all conditional types in the switch statement. From-SVN: r42404
This commit is contained in:
Geoffrey Keating
Geoffrey Keating
parent
0adc3c1971
commit
50a0b056d2
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@ -1,3 +1,34 @@
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2001-05-21 Geoff Keating <geoffk@redhat.com>
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* config/rs6000/rs6000.md (maxsf3): Use rs6000_emit_minmax.
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(maxsf3+1): Delete.
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(minsf3): Use rs6000_emit_minmax.
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(minsf3+1): Generalize to handle both SMIN and SMAX. Use
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rs6000_emit_minmax.
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(movsfcc): Use rs6000_emit_cmove.
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(fselsfsf4): Don't compare a CONST_INT with a floating-point value.
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Don't generate emit_fselsfsf4.
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(fseldfsf4): Likewise.
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(maxdf3): Use rs6000_emit_minmax.
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(maxdf3+1): Delete.
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(mindf3): Use rs6000_emit_minmax.
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(mindf3+1): Generalize to handle both SMIN and SMAX. Use
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rs6000_emit_minmax.
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(movdfcc): Use rs6000_emit_cmove.
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(fseldfdf4): Don't compare a CONST_INT with a floating-point value.
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Don't generate emit_fselsfsf4.
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(fselsfdf4): Likewise.
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* config/rs6000/rs6000.c (zero_fp_constant): New predicate.
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(min_max_operator): New predicate.
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(rs6000_emit_cmove): New function.
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(rs6000_emit_minmax): New function.
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* config/rs6000/rs6000-protos.h: Prototype new functions.
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* config/rs6000/rs6000.h (PREDICATE_CODES): Add zero_fp_constant
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and min_max_operator.
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* config/rs6000/rs6000.c (output_cbranch): Handle all
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conditional types in the switch statement.
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2001-05-21 Mark Mitchell <mark@codesourcery.com>
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* c-decl.c (finish_decl): Don't set DECL_C_HARD_REGISTER for
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@ -47,6 +47,7 @@ extern int got_operand PARAMS ((rtx, enum machine_mode));
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extern int got_no_const_operand PARAMS ((rtx, enum machine_mode));
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extern int num_insns_constant PARAMS ((rtx, enum machine_mode));
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extern int easy_fp_constant PARAMS ((rtx, enum machine_mode));
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extern int zero_fp_constant PARAMS ((rtx, enum machine_mode));
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extern int volatile_mem_operand PARAMS ((rtx, enum machine_mode));
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extern int offsettable_mem_operand PARAMS ((rtx, enum machine_mode));
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extern int mem_or_easy_const_operand PARAMS ((rtx, enum machine_mode));
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@ -79,6 +80,7 @@ extern int scc_comparison_operator PARAMS ((rtx, enum machine_mode));
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extern int trap_comparison_operator PARAMS ((rtx, enum machine_mode));
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extern int boolean_operator PARAMS ((rtx, enum machine_mode));
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extern int boolean_or_operator PARAMS ((rtx, enum machine_mode));
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extern int min_max_operator PARAMS ((rtx, enum machine_mode));
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extern int includes_lshift_p PARAMS ((rtx, rtx));
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extern int includes_rshift_p PARAMS ((rtx, rtx));
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extern int includes_lshift64_p PARAMS ((rtx, rtx));
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@ -94,6 +96,8 @@ extern enum rtx_code rs6000_reverse_condition PARAMS ((enum machine_mode,
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extern void rs6000_emit_sCOND PARAMS ((enum rtx_code, rtx));
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extern void rs6000_emit_cbranch PARAMS ((enum rtx_code, rtx));
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extern char * output_cbranch PARAMS ((rtx, const char *, int, rtx));
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extern int rs6000_emit_cmove PARAMS ((rtx, rtx, rtx, rtx));
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extern void rs6000_emit_minmax PARAMS ((rtx, enum rtx_code, rtx, rtx));
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extern void output_toc PARAMS ((FILE *, rtx, int, enum machine_mode));
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extern int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
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extern int rs6000_adjust_priority PARAMS ((rtx, int));
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@ -914,6 +914,15 @@ easy_fp_constant (op, mode)
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abort ();
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}
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/* Return 1 if the operand is 0.0. */
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int
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zero_fp_constant (op, mode)
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register rtx op;
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register enum machine_mode mode;
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{
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return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
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}
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/* Return 1 if the operand is in volatile memory. Note that during the
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RTL generation phase, memory_operand does not return TRUE for
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volatile memory references. So this function allows us to
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@ -3440,6 +3449,15 @@ boolean_or_operator (op, mode)
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enum rtx_code code = GET_CODE (op);
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return (code == IOR || code == XOR);
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}
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int
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min_max_operator (op, mode)
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rtx op;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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enum rtx_code code = GET_CODE (op);
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return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
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}
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/* Return 1 if ANDOP is a mask that has no bits on that are not in the
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mask required to convert the result of a rotate insn into a shift
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@ -4676,12 +4694,18 @@ output_cbranch (op, label, reversed, insn)
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{
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/* Not all of these are actually distinct opcodes, but
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we distinguish them for clarity of the resulting assembler. */
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case NE: ccode = "ne"; break;
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case EQ: ccode = "eq"; break;
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case GE: case GEU: ccode = "ge"; break;
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case GT: case GTU: ccode = "gt"; break;
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case LE: case LEU: ccode = "le"; break;
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case LT: case LTU: ccode = "lt"; break;
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case NE: case LTGT:
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ccode = "ne"; break;
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case EQ: case UNEQ:
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ccode = "eq"; break;
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case GE: case GEU:
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ccode = "ge"; break;
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case GT: case GTU: case UNGT:
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ccode = "gt"; break;
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case LE: case LEU:
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ccode = "le"; break;
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case LT: case LTU: case UNLT:
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ccode = "lt"; break;
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case UNORDERED: ccode = "un"; break;
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case ORDERED: ccode = "nu"; break;
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case UNGE: ccode = "nl"; break;
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@ -4731,6 +4755,181 @@ output_cbranch (op, label, reversed, insn)
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return string;
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}
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/* Emit a conditional move: move TRUE_COND to DEST if OP of the
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operands of the last comparison is nonzero/true, FALSE_COND if it
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is zero/false. Return 0 if the hardware has no such operation. */
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int
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rs6000_emit_cmove (dest, op, true_cond, false_cond)
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rtx dest;
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rtx op;
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rtx true_cond;
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rtx false_cond;
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{
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enum rtx_code code = GET_CODE (op);
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rtx op0 = rs6000_compare_op0;
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rtx op1 = rs6000_compare_op1;
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REAL_VALUE_TYPE c1;
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enum machine_mode mode = GET_MODE (op0);
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rtx temp;
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/* First, work out if the hardware can do this at all, or
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if it's too slow... */
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/* If the comparison is an integer one, since we only have fsel
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it'll be cheaper to use a branch. */
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if (! rs6000_compare_fp_p)
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return 0;
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/* Eliminate half of the comparisons by switching operands, this
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makes the remaining code simpler. */
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if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
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|| code == LTGT || code == LT)
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{
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code = reverse_condition_maybe_unordered (code);
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temp = true_cond;
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true_cond = false_cond;
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false_cond = temp;
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}
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/* UNEQ and LTGT take four instructions for a comparison with zero,
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it'll probably be faster to use a branch here too. */
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if (code == UNEQ)
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return 0;
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if (GET_CODE (op1) == CONST_DOUBLE)
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REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
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/* We're going to try to implement comparions by performing
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a subtract, then comparing against zero. Unfortunately,
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Inf - Inf is NaN which is not zero, and so if we don't
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know that the the operand is finite and the comparison
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would treat EQ different to UNORDERED, we can't do it. */
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if (! flag_unsafe_math_optimizations
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&& code != GT && code != UNGE
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&& (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1))
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/* Constructs of the form (a OP b ? a : b) are safe. */
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&& ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
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|| (! rtx_equal_p (op0, true_cond)
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&& ! rtx_equal_p (op1, true_cond))))
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return 0;
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/* At this point we know we can use fsel. */
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/* Reduce the comparison to a comparison against zero. */
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp,
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gen_rtx_MINUS (mode, op0, op1)));
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op0 = temp;
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op1 = CONST0_RTX (mode);
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/* If we don't care about NaNs we can reduce some of the comparisons
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down to faster ones. */
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if (flag_unsafe_math_optimizations)
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switch (code)
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{
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case GT:
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code = LE;
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temp = true_cond;
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true_cond = false_cond;
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false_cond = temp;
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break;
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case UNGE:
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code = GE;
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break;
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case UNEQ:
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code = EQ;
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break;
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default:
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break;
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}
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/* Now, reduce everything down to a GE. */
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switch (code)
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{
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case GE:
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break;
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case LE:
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
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op0 = temp;
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break;
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case ORDERED:
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (mode, op0)));
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op0 = temp;
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break;
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case EQ:
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp,
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gen_rtx_NEG (mode,
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gen_rtx_ABS (mode, op0))));
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op0 = temp;
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break;
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case UNGE:
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp,
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gen_rtx_IF_THEN_ELSE (mode,
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gen_rtx_GE (VOIDmode,
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op0, op1),
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true_cond, false_cond)));
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false_cond = temp;
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true_cond = false_cond;
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
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op0 = temp;
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break;
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case GT:
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp,
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gen_rtx_IF_THEN_ELSE (mode,
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gen_rtx_GE (VOIDmode,
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op0, op1),
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true_cond, false_cond)));
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true_cond = temp;
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false_cond = true_cond;
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temp = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (mode, op0)));
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op0 = temp;
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break;
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default:
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abort ();
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}
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emit_insn (gen_rtx_SET (VOIDmode, dest,
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gen_rtx_IF_THEN_ELSE (mode,
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gen_rtx_GE (VOIDmode,
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op0, op1),
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true_cond, false_cond)));
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return 1;
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}
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void
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rs6000_emit_minmax (dest, code, op0, op1)
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rtx dest;
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enum rtx_code code;
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rtx op0;
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rtx op1;
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{
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enum machine_mode mode = GET_MODE (op0);
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rtx target;
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if (code == SMAX || code == UMAX)
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target = emit_conditional_move (dest, GE, op0, op1, mode,
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op0, op1, mode, 0);
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else
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target = emit_conditional_move (dest, GE, op0, op1, mode,
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op1, op0, mode, 0);
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if (target == NULL_RTX)
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abort ();
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if (target != dest)
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emit_move_insn (dest, target);
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}
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/* This page contains routines that are used to determine what the function
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prologue and epilogue code will do and write them out. */
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|
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@ -2683,6 +2683,7 @@ do { \
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{"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
|
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{"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
|
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{"easy_fp_constant", {CONST_DOUBLE}}, \
|
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{"zero_fp_constant", {CONST_DOUBLE}}, \
|
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{"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
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{"lwa_operand", {SUBREG, MEM, REG}}, \
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{"volatile_mem_operand", {MEM}}, \
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|
|
@ -2718,7 +2719,8 @@ do { \
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{"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
|
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GT, LEU, LTU, GEU, GTU}}, \
|
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{"boolean_operator", {AND, IOR, XOR}}, \
|
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{"boolean_or_operator", {IOR, XOR}},
|
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{"boolean_or_operator", {IOR, XOR}}, \
|
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{"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
|
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|
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/* uncomment for disabling the corresponding default options */
|
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/* #define MACHINE_no_sched_interblock */
|
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|
|
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|
@ -4822,60 +4822,35 @@
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;; single DEFINE_INSN for fsel and the define_splits to make them if made by
|
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;; combine.
|
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(define_expand "maxsf3"
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[(set (match_dup 3)
|
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(minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
|
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(match_operand:SF 2 "gpc_reg_operand" "")))
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(set (match_operand:SF 0 "gpc_reg_operand" "")
|
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(if_then_else:SF (ge (match_dup 3)
|
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(const_int 0))
|
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(match_dup 1)
|
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(match_dup 2)))]
|
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"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
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"
|
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{ operands[3] = gen_reg_rtx (SFmode); }")
|
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|
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(define_split
|
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
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(smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
|
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(match_operand:SF 2 "gpc_reg_operand" "")))
|
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(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
|
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"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
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[(set (match_dup 3)
|
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(minus:SF (match_dup 1) (match_dup 2)))
|
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(set (match_dup 0)
|
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(if_then_else:SF (ge (match_dup 3)
|
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(const_int 0))
|
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(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
|
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(match_operand:SF 2 "gpc_reg_operand" ""))
|
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(match_dup 1)
|
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(match_dup 2)))]
|
||||
"")
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
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"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
|
||||
|
||||
(define_expand "minsf3"
|
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[(set (match_dup 3)
|
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(minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
|
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(match_operand:SF 1 "gpc_reg_operand" "")))
|
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(set (match_operand:SF 0 "gpc_reg_operand" "")
|
||||
(if_then_else:SF (ge (match_dup 3)
|
||||
(const_int 0))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
||||
(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
|
||||
(match_operand:SF 2 "gpc_reg_operand" ""))
|
||||
(match_dup 2)
|
||||
(match_dup 1)))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"
|
||||
{ operands[3] = gen_reg_rtx (SFmode); }")
|
||||
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
||||
(smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
|
||||
(match_operand:SF 2 "gpc_reg_operand" "")))
|
||||
(clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
|
||||
(match_operator:SF 3 "min_max_operator"
|
||||
[(match_operand:SF 1 "gpc_reg_operand" "")
|
||||
(match_operand:SF 2 "gpc_reg_operand" "")]))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
[(set (match_dup 3)
|
||||
(minus:SF (match_dup 2) (match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(if_then_else:SF (ge (match_dup 3)
|
||||
(const_int 0))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"")
|
||||
[(const_int 0)]
|
||||
"
|
||||
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
|
||||
operands[1], operands[2]);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "movsfcc"
|
||||
[(set (match_operand:SF 0 "gpc_reg_operand" "")
|
||||
|
|
@ -4885,72 +4860,26 @@
|
|||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"
|
||||
{
|
||||
rtx temp, op0, op1;
|
||||
enum rtx_code code = GET_CODE (operands[1]);
|
||||
if (! rs6000_compare_fp_p)
|
||||
FAIL;
|
||||
switch (code)
|
||||
{
|
||||
case GE: case EQ:
|
||||
op0 = rs6000_compare_op0;
|
||||
op1 = rs6000_compare_op1;
|
||||
break;
|
||||
case GT:
|
||||
op0 = rs6000_compare_op1;
|
||||
op1 = rs6000_compare_op0;
|
||||
temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
|
||||
break;
|
||||
case LE:
|
||||
op0 = rs6000_compare_op1;
|
||||
op1 = rs6000_compare_op0;
|
||||
break;
|
||||
case LT:
|
||||
op0 = rs6000_compare_op0;
|
||||
op1 = rs6000_compare_op1;
|
||||
temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
|
||||
break;
|
||||
default:
|
||||
FAIL;
|
||||
}
|
||||
if (GET_MODE (rs6000_compare_op0) == DFmode)
|
||||
{
|
||||
temp = gen_reg_rtx (DFmode);
|
||||
emit_insn (gen_subdf3 (temp, op0, op1));
|
||||
emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
|
||||
if (code == EQ)
|
||||
{
|
||||
emit_insn (gen_negdf2 (temp, temp));
|
||||
emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
|
||||
}
|
||||
}
|
||||
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
||||
DONE;
|
||||
else
|
||||
{
|
||||
temp = gen_reg_rtx (SFmode);
|
||||
emit_insn (gen_subsf3 (temp, op0, op1));
|
||||
emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
|
||||
if (code == EQ)
|
||||
{
|
||||
emit_insn (gen_negsf2 (temp, temp));
|
||||
emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
|
||||
}
|
||||
}
|
||||
DONE;
|
||||
FAIL;
|
||||
}")
|
||||
|
||||
(define_insn "fselsfsf4"
|
||||
(define_insn "*fselsfsf4"
|
||||
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
||||
(if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
|
||||
(const_int 0))
|
||||
(match_operand:SF 4 "zero_fp_constant" "F"))
|
||||
(match_operand:SF 2 "gpc_reg_operand" "f")
|
||||
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"fsel %0,%1,%2,%3"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
(define_insn "fseldfsf4"
|
||||
(define_insn "*fseldfsf4"
|
||||
[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
|
||||
(if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
|
||||
(const_int 0))
|
||||
(match_operand:SF 4 "zero_fp_constant" "F"))
|
||||
(match_operand:SF 2 "gpc_reg_operand" "f")
|
||||
(match_operand:SF 3 "gpc_reg_operand" "f")))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
|
|
@ -5053,66 +4982,39 @@
|
|||
"fsqrt %0,%1"
|
||||
[(set_attr "type" "dsqrt")])
|
||||
|
||||
;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
|
||||
;; fsel instruction and some auxiliary computations. Then we just have a
|
||||
;; single DEFINE_INSN for fsel and the define_splits to make them if made by
|
||||
;; combine.
|
||||
;; The conditional move instructions allow us to perform max and min
|
||||
;; operations even when
|
||||
|
||||
(define_expand "maxdf3"
|
||||
[(set (match_dup 3)
|
||||
(minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
||||
(match_operand:DF 2 "gpc_reg_operand" "")))
|
||||
(set (match_operand:DF 0 "gpc_reg_operand" "")
|
||||
(if_then_else:DF (ge (match_dup 3)
|
||||
(const_int 0))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"
|
||||
{ operands[3] = gen_reg_rtx (DFmode); }")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
||||
(smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
||||
(match_operand:DF 2 "gpc_reg_operand" "")))
|
||||
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
[(set (match_dup 3)
|
||||
(minus:DF (match_dup 1) (match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(if_then_else:DF (ge (match_dup 3)
|
||||
(const_int 0))
|
||||
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
|
||||
(match_operand:DF 2 "gpc_reg_operand" ""))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"")
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
|
||||
|
||||
(define_expand "mindf3"
|
||||
[(set (match_dup 3)
|
||||
(minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
|
||||
(match_operand:DF 1 "gpc_reg_operand" "")))
|
||||
(set (match_operand:DF 0 "gpc_reg_operand" "")
|
||||
(if_then_else:DF (ge (match_dup 3)
|
||||
(const_int 0))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
||||
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
|
||||
(match_operand:DF 2 "gpc_reg_operand" ""))
|
||||
(match_dup 2)
|
||||
(match_dup 1)))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"
|
||||
{ operands[3] = gen_reg_rtx (DFmode); }")
|
||||
"{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
||||
(smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
|
||||
(match_operand:DF 2 "gpc_reg_operand" "")))
|
||||
(clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
|
||||
(match_operator:DF 3 "min_max_operator"
|
||||
[(match_operand:DF 1 "gpc_reg_operand" "")
|
||||
(match_operand:DF 2 "gpc_reg_operand" "")]))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
[(set (match_dup 3)
|
||||
(minus:DF (match_dup 2) (match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(if_then_else:DF (ge (match_dup 3)
|
||||
(const_int 0))
|
||||
(match_dup 1)
|
||||
(match_dup 2)))]
|
||||
"")
|
||||
[(const_int 0)]
|
||||
"
|
||||
{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
|
||||
operands[1], operands[2]);
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_expand "movdfcc"
|
||||
[(set (match_operand:DF 0 "gpc_reg_operand" "")
|
||||
|
|
@ -5122,72 +5024,26 @@
|
|||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"
|
||||
{
|
||||
rtx temp, op0, op1;
|
||||
enum rtx_code code = GET_CODE (operands[1]);
|
||||
if (! rs6000_compare_fp_p)
|
||||
FAIL;
|
||||
switch (code)
|
||||
{
|
||||
case GE: case EQ:
|
||||
op0 = rs6000_compare_op0;
|
||||
op1 = rs6000_compare_op1;
|
||||
break;
|
||||
case GT:
|
||||
op0 = rs6000_compare_op1;
|
||||
op1 = rs6000_compare_op0;
|
||||
temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
|
||||
break;
|
||||
case LE:
|
||||
op0 = rs6000_compare_op1;
|
||||
op1 = rs6000_compare_op0;
|
||||
break;
|
||||
case LT:
|
||||
op0 = rs6000_compare_op0;
|
||||
op1 = rs6000_compare_op1;
|
||||
temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
|
||||
break;
|
||||
default:
|
||||
FAIL;
|
||||
}
|
||||
if (GET_MODE (rs6000_compare_op0) == DFmode)
|
||||
{
|
||||
temp = gen_reg_rtx (DFmode);
|
||||
emit_insn (gen_subdf3 (temp, op0, op1));
|
||||
emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
|
||||
if (code == EQ)
|
||||
{
|
||||
emit_insn (gen_negdf2 (temp, temp));
|
||||
emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
|
||||
}
|
||||
}
|
||||
if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
|
||||
DONE;
|
||||
else
|
||||
{
|
||||
temp = gen_reg_rtx (SFmode);
|
||||
emit_insn (gen_subsf3 (temp, op0, op1));
|
||||
emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
|
||||
if (code == EQ)
|
||||
{
|
||||
emit_insn (gen_negsf2 (temp, temp));
|
||||
emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
|
||||
}
|
||||
}
|
||||
DONE;
|
||||
FAIL;
|
||||
}")
|
||||
|
||||
(define_insn "fseldfdf4"
|
||||
(define_insn "*fseldfdf4"
|
||||
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
||||
(if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
|
||||
(const_int 0))
|
||||
(match_operand:DF 4 "zero_fp_constant" "F"))
|
||||
(match_operand:DF 2 "gpc_reg_operand" "f")
|
||||
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
||||
"TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
|
||||
"fsel %0,%1,%2,%3"
|
||||
[(set_attr "type" "fp")])
|
||||
|
||||
(define_insn "fselsfdf4"
|
||||
(define_insn "*fselsfdf4"
|
||||
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
|
||||
(if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
|
||||
(const_int 0))
|
||||
(match_operand:SF 4 "zero_fp_constant" "F"))
|
||||
(match_operand:DF 2 "gpc_reg_operand" "f")
|
||||
(match_operand:DF 3 "gpc_reg_operand" "f")))]
|
||||
"TARGET_PPC_GFXOPT"
|
||||
|
|
|
|||
Loading…
Reference in New Issue