MIPS SB-1 DFA scheduler.
* config/mips/mips-protos.h (fp_register_operand, lo_operand): Declare. * config/mips/mips.c (mips_multipass_dfa_lookahead): Declare. (TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): New. (fp_register_operand, lo_operand): New. (mips_rtx_costs): Add TUNE_SB1 support. (mips_issue_rate): Add comment. Add PROCESSOR_SB1 support. (mips_use_dfa_pipeline_interface): Add PROCESSOR_SB1 support. (mips_multipass_dfa_lookahead): New. * config/mips/mips.h (MASK_FP_EXCEPTIONS, TARGET_FP_EXCEPTIONS, TUNE_SB1): New. (TARGET_SWITCHES): Add -mfp-exceptions support. (TARGET_FP_EXCEPTIONS_DEFAULT): New. (BRANCH_COST): Fix whitespace. * config/mips/mips.md: Include sb1.md. * config/mips/sb1.md: New file. * doc/invoke.texi: Document -mfp-exceptions. From-SVN: r80988
This commit is contained in:
James E Wilson
Jim Wilson
parent
e24e0aa7fb
commit
50d32cf64c
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@ -10,6 +10,23 @@
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2004-04-21 James E Wilson <wilson@specifixinc.com>
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* config/mips/mips-protos.h (fp_register_operand, lo_operand): Declare.
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* config/mips/mips.c (mips_multipass_dfa_lookahead): Declare.
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(TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD): New.
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(fp_register_operand, lo_operand): New.
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(mips_rtx_costs): Add TUNE_SB1 support.
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(mips_issue_rate): Add comment. Add PROCESSOR_SB1 support.
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(mips_use_dfa_pipeline_interface): Add PROCESSOR_SB1 support.
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(mips_multipass_dfa_lookahead): New.
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* config/mips/mips.h (MASK_FP_EXCEPTIONS, TARGET_FP_EXCEPTIONS,
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TUNE_SB1): New.
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(TARGET_SWITCHES): Add -mfp-exceptions support.
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(TARGET_FP_EXCEPTIONS_DEFAULT): New.
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(BRANCH_COST): Fix whitespace.
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* config/mips/mips.md: Include sb1.md.
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* config/mips/sb1.md: New file.
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* doc/invoke.texi: Document -mfp-exceptions.
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* Makefile.in (fixinc.sh): Don't set or export WARN_CFLAGS. Fix
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comment.
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* fixinc/Makefile.in (FL_LIST): Don't mention WARN_CFLAGS.
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@ -93,6 +93,8 @@ extern int mips_address_insns (rtx, enum machine_mode);
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extern int mips_const_insns (rtx);
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extern int mips_fetch_insns (rtx);
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extern int mips_idiv_insns (void);
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extern int fp_register_operand (rtx, enum machine_mode);
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extern int lo_operand (rtx, enum machine_mode);
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extern bool mips_legitimate_address_p (enum machine_mode, rtx, int);
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extern rtx mips_unspec_address (rtx, enum mips_symbol_type);
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extern bool mips_legitimize_address (rtx *, enum machine_mode);
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@ -232,6 +232,7 @@ static bool mips_return_in_memory (tree, tree);
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static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
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static int mips_issue_rate (void);
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static int mips_use_dfa_pipeline_interface (void);
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static int mips_multipass_dfa_lookahead (void);
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static void mips_init_libfuncs (void);
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static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
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tree, int *, int);
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@ -680,6 +681,9 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
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#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
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#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
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#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
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#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
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#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
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mips_multipass_dfa_lookahead
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#undef TARGET_FUNCTION_OK_FOR_SIBCALL
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#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
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@ -1661,6 +1665,23 @@ stack_operand (rtx op, enum machine_mode mode)
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&& addr.reg == stack_pointer_rtx);
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}
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/* Helper function for DFA schedulers. Return true if OP is a floating
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point register. */
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int
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fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return REG_P (op) && FP_REG_P (REGNO (op));
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}
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/* Helper function for DFA schedulers. Return true if OP is a LO reg. */
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int
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lo_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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return REG_P (op) && REGNO (op) == LO_REGNUM;
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}
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/* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
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returns a nonzero value if X is a legitimate address for a memory
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@ -2265,6 +2286,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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*total = COSTS_N_INSNS (2);
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else if (TUNE_MIPS6000)
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*total = COSTS_N_INSNS (3);
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else if (TUNE_SB1)
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*total = COSTS_N_INSNS (4);
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else
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*total = COSTS_N_INSNS (6);
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return true;
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@ -2289,7 +2312,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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{
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if (TUNE_MIPS3000
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|| TUNE_MIPS3900
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|| TUNE_MIPS5000)
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|| TUNE_MIPS5000
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|| TUNE_SB1)
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*total = COSTS_N_INSNS (4);
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else if (TUNE_MIPS6000
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|| TUNE_MIPS5400
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@ -2302,7 +2326,9 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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if (mode == DFmode)
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{
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if (TUNE_MIPS3000
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if (TUNE_SB1)
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*total = COSTS_N_INSNS (4);
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else if (TUNE_MIPS3000
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|| TUNE_MIPS3900
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|| TUNE_MIPS5000)
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*total = COSTS_N_INSNS (5);
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@ -2319,7 +2345,7 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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*total = COSTS_N_INSNS (12);
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else if (TUNE_MIPS3900)
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*total = COSTS_N_INSNS (2);
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else if (TUNE_MIPS5400 || TUNE_MIPS5500)
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else if (TUNE_MIPS5400 || TUNE_MIPS5500 || TUNE_SB1)
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*total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
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else if (TUNE_MIPS7000)
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*total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
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@ -2342,6 +2368,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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*total = COSTS_N_INSNS (12);
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else if (TUNE_MIPS6000)
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*total = COSTS_N_INSNS (15);
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else if (TUNE_SB1)
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*total = COSTS_N_INSNS (24);
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else if (TUNE_MIPS5400 || TUNE_MIPS5500)
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*total = COSTS_N_INSNS (30);
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else
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@ -2358,6 +2386,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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*total = COSTS_N_INSNS (59);
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else if (TUNE_MIPS6000)
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*total = COSTS_N_INSNS (16);
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else if (TUNE_SB1)
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*total = COSTS_N_INSNS (32);
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else
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*total = COSTS_N_INSNS (36);
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return true;
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@ -2373,6 +2403,8 @@ mips_rtx_costs (rtx x, int code, int outer_code, int *total)
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*total = COSTS_N_INSNS (38);
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else if (TUNE_MIPS5000)
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*total = COSTS_N_INSNS (36);
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else if (TUNE_SB1)
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*total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
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else if (TUNE_MIPS5400 || TUNE_MIPS5500)
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*total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
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else
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@ -9292,6 +9324,8 @@ mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
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{
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return !TARGET_OLDABI;
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}
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/* Return the number of instructions that can be issued per cycle. */
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static int
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mips_issue_rate (void)
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@ -9304,6 +9338,13 @@ mips_issue_rate (void)
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case PROCESSOR_R9000:
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return 2;
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case PROCESSOR_SB1:
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/* This is actually 4, but we get better performance if we claim 3.
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This is partly because of unwanted speculative code motion with the
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larger number, and partly because in most common cases we can't
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reach the theoretical max of 4. */
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return 3;
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default:
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return 1;
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}
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@ -9324,6 +9365,7 @@ mips_use_dfa_pipeline_interface (void)
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case PROCESSOR_R5500:
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case PROCESSOR_R7000:
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case PROCESSOR_R9000:
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case PROCESSOR_SB1:
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case PROCESSOR_SR71000:
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return true;
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@ -9332,6 +9374,19 @@ mips_use_dfa_pipeline_interface (void)
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}
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}
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/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
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be as wide as the scheduling freedom in the DFA. */
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static int
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mips_multipass_dfa_lookahead (void)
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{
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/* Can schedule up to 4 of the 6 function units in any one cycle. */
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if (mips_tune == PROCESSOR_SB1)
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return 4;
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return 0;
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}
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const char *
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mips_emit_prefetch (rtx *operands)
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@ -173,6 +173,8 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define MASK_FIX_SB1 0x04000000 /* Work around SB-1 errata. */
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#define MASK_FIX_VR4120 0x08000000 /* Work around VR4120 errata. */
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#define MASK_FP_EXCEPTIONS 0x10000000 /* FP exceptions are enabled. */
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/* Debug switches, not documented */
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#define MASK_DEBUG 0 /* unused */
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#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
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@ -257,6 +259,8 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define TARGET_FIX_R4400 (target_flags & MASK_FIX_R4400)
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#define TARGET_FIX_VR4120 (target_flags & MASK_FIX_VR4120)
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#define TARGET_FP_EXCEPTIONS (target_flags & MASK_FP_EXCEPTIONS)
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/* True if we should use NewABI-style relocation operators for
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symbolic addresses. This is never true for mips16 code,
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which has its own conventions. */
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@ -339,6 +343,7 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
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#define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
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#define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
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#define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
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#define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
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#define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
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@ -630,6 +635,10 @@ extern const struct mips_cpu_info *mips_tune_info;
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N_("Lift restrictions on GOT size") }, \
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{"no-xgot", -MASK_XGOT, \
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N_("Do not lift restrictions on GOT size") }, \
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{"fp-exceptions", MASK_FP_EXCEPTIONS, \
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N_("FP exceptions are enabled") }, \
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{"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
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N_("FP exceptions are not enabled") }, \
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{"debug", MASK_DEBUG, \
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NULL}, \
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{"debugc", MASK_DEBUG_C, \
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@ -640,7 +649,8 @@ extern const struct mips_cpu_info *mips_tune_info;
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NULL}, \
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{"", (TARGET_DEFAULT \
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| TARGET_CPU_DEFAULT \
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| TARGET_ENDIAN_DEFAULT), \
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| TARGET_ENDIAN_DEFAULT \
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| TARGET_FP_EXCEPTIONS_DEFAULT), \
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NULL}, \
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}
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@ -658,6 +668,10 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
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#endif
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#ifndef TARGET_FP_EXCEPTIONS_DEFAULT
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#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
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#endif
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/* 'from-abi' makes a good default: you get whatever the ABI requires. */
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#ifndef MIPS_ISA_DEFAULT
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#ifndef MIPS_CPU_STRING_DEFAULT
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@ -2674,7 +2688,7 @@ typedef struct mips_args {
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/* ??? Fix this to be right for the R8000. */
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#define BRANCH_COST \
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((! TARGET_MIPS16 \
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&& (TUNE_MIPS4000 || TUNE_MIPS6000)) \
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&& (TUNE_MIPS4000 || TUNE_MIPS6000)) \
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? 2 : 1)
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/* If defined, modifies the length assigned to instruction INSN as a
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@ -628,6 +628,7 @@
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(include "5500.md")
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(include "7000.md")
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(include "9000.md")
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(include "sb1.md")
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(include "sr71k.md")
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;;
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@ -0,0 +1,504 @@
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;;
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;; DFA-based pipeline description for Broadcom SB-1
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;;
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;; The Broadcom SB-1 core is 4-way superscalar, in-order. It has 2 load/store
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;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP
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;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns
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;; each cycle.
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;; We model the 4-way issue by ordering unit choices. The possible choices are
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;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit
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;; in the list in most cases. Non-indexed load/stores issue to ls0 first.
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;; simple alu operations issue to ls1 if it is still available, and their
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;; operands are ready (no co-issue with loads), otherwise to the first
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;; available ex unit.
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;; When exceptions are enabled, can only issue FP insns to fp1. This is
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;; to ensure that instructions complete in order. The -mfp-exceptions option
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;; can be used to specify whether the system has FP exceptions enabled or not.
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;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe
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;; insn can issue per cycle (fp1).
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;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register
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;; file. As a result, once an MDMX insn is issued, no FP insns can be issued
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;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for
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;; 5 cycles. This is currently not handled because there is no MDMX insn
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;; support as yet.
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;;
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;; We use two automata. sb1_cpu_div is for the integer divides, which are
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;; not pipelined. sb1_cpu is for everything else.
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;;
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(define_automaton "sb1_cpu, sb1_cpu_div")
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;; Load/store function units.
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(define_cpu_unit "sb1_ls0" "sb1_cpu")
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(define_cpu_unit "sb1_ls1" "sb1_cpu")
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;; CPU function units.
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(define_cpu_unit "sb1_ex0" "sb1_cpu")
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(define_cpu_unit "sb1_ex1" "sb1_cpu")
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;; The divide unit is not pipelined, and blocks hi/lo reads and writes.
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(define_cpu_unit "sb1_div" "sb1_cpu_div")
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;; DMULT block any multiply from issuing in the next cycle.
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(define_cpu_unit "sb1_mul" "sb1_cpu")
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;; Floating-point units.
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(define_cpu_unit "sb1_fp0" "sb1_cpu")
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(define_cpu_unit "sb1_fp1" "sb1_cpu")
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;; Can only issue to one of the ex and fp pipes at a time.
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(exclusion_set "sb1_ex0" "sb1_fp0")
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(exclusion_set "sb1_ex1" "sb1_fp1")
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;; Define an SB-1 specific attribute to simplify some FP descriptions.
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;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are
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;; disabled.
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(define_attr "sb1_fp_pipes" "one,two"
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(cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0))
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(eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0)))
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(const_string "two")]
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(const_string "one")))
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;; Define reservations for common combinations.
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;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats,
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;; effectively re-issuing the operation every 4 cycles. This means that we
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;; can have at most 4 long-cycle operations per pipe.
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;; ??? The fdiv operations should be e.g.
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;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7
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;; but the DFA is too large when we do that. Perhaps have to use scheduler
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;; hooks here.
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;; ??? Try limiting scheduler to 2 long latency operations, and see if this
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;; results in a usable DFA, and whether it helps code performance.
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;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3")
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;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3")
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;;
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;; The ordering of the instruction-execution-path/resource-usage
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;; descriptions (also known as reservation RTL) is roughly ordered
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;; based on the define attribute RTL for the "type" classification.
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;; When modifying, remember that the first test that matches is the
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;; reservation used!
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;;
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(define_insn_reservation "ir_sb1_unknown" 1
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(and (eq_attr "cpu" "sb1")
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(eq_attr "type" "unknown,multi"))
|
||||
"sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1")
|
||||
|
||||
;; predicted taken branch causes 2 cycle ifetch bubble. predicted not
|
||||
;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8
|
||||
;; cycle ifetch bubble. We assume all branches predicted not taken.
|
||||
|
||||
;; ??? This assumption that branches are predicated not taken should be
|
||||
;; investigated. Maybe using 2 here will give better results.
|
||||
|
||||
(define_insn_reservation "ir_sb1_branch" 0
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "branch,jump,call"))
|
||||
"sb1_ex0")
|
||||
|
||||
;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
|
||||
;; register as destination.
|
||||
|
||||
;; ??? Can co-issue a load with a dependent arith insn if it executes on an EX
|
||||
;; unit. Can not co-issue if the dependent insn executes on an LS unit.
|
||||
|
||||
;; A load normally has a latency of zero cycles. In some cases, dependent
|
||||
;; insns can be issued in the same cycle. However, a value of 1 gives
|
||||
;; better performance in empirical testing.
|
||||
|
||||
(define_insn_reservation "ir_sb1_load" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "load,prefetch"))
|
||||
"sb1_ls0 | sb1_ls1")
|
||||
|
||||
;; Can not co-issue fpload with fp exe when in 32-bit mode.
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpload" 0
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fpload")
|
||||
(ne (symbol_ref "TARGET_FLOAT64")
|
||||
(const_int 0))))
|
||||
"sb1_ls0 | sb1_ls1")
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpload_32bitfp" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fpload")
|
||||
(eq (symbol_ref "TARGET_FLOAT64")
|
||||
(const_int 0))))
|
||||
"sb1_ls0 | sb1_ls1")
|
||||
|
||||
;; Indexed loads can only execute on LS1 pipe.
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpidxload" 0
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fpidxload")
|
||||
(ne (symbol_ref "TARGET_FLOAT64")
|
||||
(const_int 0))))
|
||||
"sb1_ls1")
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fpidxload")
|
||||
(eq (symbol_ref "TARGET_FLOAT64")
|
||||
(const_int 0))))
|
||||
"sb1_ls1")
|
||||
|
||||
;; prefx can only execute on the ls1 pipe.
|
||||
|
||||
(define_insn_reservation "ir_sb1_prefetchx" 0
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "prefetchx"))
|
||||
"sb1_ls1")
|
||||
|
||||
;; ??? There is a 4.5 cycle latency if a store is followed by a load, and
|
||||
;; there is a RAW dependency.
|
||||
|
||||
(define_insn_reservation "ir_sb1_store" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "store"))
|
||||
"sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpstore" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "fpstore"))
|
||||
"sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
|
||||
|
||||
;; Indexed stores can only execute on LS1 pipe.
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpidxstore" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "fpidxstore"))
|
||||
"sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0")
|
||||
|
||||
;; Load latencies are 3 cycles for one load to another load or store (address
|
||||
;; only). This is 0 cycles for one load to a store using it as the data
|
||||
;; written.
|
||||
|
||||
;; This assumes that if a load is dependent on a previous insn, then it must
|
||||
;; be an address dependence.
|
||||
|
||||
(define_bypass 3
|
||||
"ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
|
||||
ir_sb1_fpidxload_32bitfp"
|
||||
"ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
|
||||
ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
|
||||
|
||||
(define_bypass 3
|
||||
"ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
|
||||
ir_sb1_fpidxload_32bitfp"
|
||||
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
|
||||
"store_data_bypass_p")
|
||||
|
||||
;; Simple alu instructions can execute on the LS1 unit.
|
||||
|
||||
;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
|
||||
;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to
|
||||
;; another LS insn (excluding store data). A simple alu insn issued on an EX
|
||||
;; unit has a latency of 5 cycles when the results goes to a LS unit (exluding
|
||||
;; store data), otherwise a latency of 1 cycle.
|
||||
|
||||
;; ??? We can not handle latencies properly for simple alu instructions
|
||||
;; within the DFA pipeline model. Latencies can be defined only from one
|
||||
;; insn reservation to another. We can't make them depend on which function
|
||||
;; unit was used. This isn't a DFA flaw. There is a conflict here, as we
|
||||
;; need to know the latency before we can determine which unit will be
|
||||
;; available, but we need to know which unit it is issued to before we can
|
||||
;; compute the latency. Perhaps this can be handled via scheduler hooks.
|
||||
;; This needs to be investigated.
|
||||
|
||||
;; ??? Optimal scheduling taking the LS units into account seems to require
|
||||
;; a pre-scheduling pass. We need to determine which instructions feed results
|
||||
;; into store/load addresses, and thus benefit most from being issued to the
|
||||
;; LS unit. Also, we need to prune the list to ensure we don't overschedule
|
||||
;; insns to the LS unit, and that we don't conflict with insns that need LS1
|
||||
;; such as indexed loads. We then need to emit nops to ensure that simple
|
||||
;; alu instructions that are not supposed to be scheduled to LS1 don't
|
||||
;; accidentally end up there because LS1 is free when they are issued. This
|
||||
;; will be a lot of work, and it isn't clear how useful it will be.
|
||||
|
||||
;; Empirical testing shows that 2 gives the best result.
|
||||
|
||||
(define_insn_reservation "ir_sb1_simple_alu" 2
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "const,arith"))
|
||||
"sb1_ls1 | sb1_ex1 | sb1_ex0")
|
||||
|
||||
;; ??? condmove also includes some FP instructions that execute on the FP
|
||||
;; units. This needs to be clarified.
|
||||
|
||||
(define_insn_reservation "ir_sb1_alu" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "condmove,nop,shift"))
|
||||
"sb1_ex1 | sb1_ex0")
|
||||
|
||||
;; These are type arith/darith that only execute on the EX0 unit.
|
||||
|
||||
(define_insn_reservation "ir_sb1_alu_0" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "slt,clz,trap"))
|
||||
"sb1_ex0")
|
||||
|
||||
;; An alu insn issued on an EX unit has a latency of 5 cycles when the
|
||||
;; result goes to a LS unit (excluding store data).
|
||||
|
||||
;; This assumes that if a load is dependent on a previous insn, then it must
|
||||
;; be an address dependence.
|
||||
|
||||
(define_bypass 5
|
||||
"ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
|
||||
"ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
|
||||
ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
|
||||
|
||||
(define_bypass 5
|
||||
"ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
|
||||
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
|
||||
"store_data_bypass_p")
|
||||
|
||||
;; mf{hi,lo} is 1 cycle.
|
||||
|
||||
(define_insn_reservation "ir_sb1_mfhi" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "mfhilo")
|
||||
(not (match_operand 1 "lo_operand" ""))))
|
||||
"sb1_ex1")
|
||||
|
||||
(define_insn_reservation "ir_sb1_mflo" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "mfhilo")
|
||||
(match_operand 1 "lo_operand" "")))
|
||||
"sb1_ex1")
|
||||
|
||||
;; mt{hi,lo} to mul/div is 4 cycles.
|
||||
|
||||
(define_insn_reservation "ir_sb1_mthilo" 4
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "mthilo"))
|
||||
"sb1_ex1")
|
||||
|
||||
;; mt{hi,lo} to mf{hi,lo} is 3 cycles.
|
||||
|
||||
(define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo")
|
||||
|
||||
;; multiply latency to an EX operation is 3 cycles.
|
||||
|
||||
;; ??? Should check whether we need to make multiply conflict with moves
|
||||
;; to/from hilo registers.
|
||||
|
||||
(define_insn_reservation "ir_sb1_mulsi" 3
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "imul,imadd")
|
||||
(eq_attr "mode" "SI")))
|
||||
"sb1_ex1+sb1_mul")
|
||||
|
||||
;; muldi to mfhi is 4 cycles.
|
||||
;; Blocks any other multiply insn issue for 1 cycle.
|
||||
|
||||
(define_insn_reservation "ir_sb1_muldi" 4
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "imul")
|
||||
(eq_attr "mode" "DI")))
|
||||
"sb1_ex1+sb1_mul, sb1_mul")
|
||||
|
||||
;; muldi to mflo is 3 cycles.
|
||||
|
||||
(define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo")
|
||||
|
||||
;; mul latency is 7 cycles if the result is used by any LS insn.
|
||||
|
||||
;; This assumes that if a load is dependent on a previous insn, then it must
|
||||
;; be an address dependence.
|
||||
|
||||
(define_bypass 7
|
||||
"ir_sb1_mulsi,ir_sb1_muldi"
|
||||
"ir_sb1_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,ir_sb1_fpidxload,
|
||||
ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
|
||||
|
||||
(define_bypass 7
|
||||
"ir_sb1_mulsi,ir_sb1_muldi"
|
||||
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
|
||||
"store_data_bypass_p")
|
||||
|
||||
;; The divide unit is not pipelined. Divide busy is asserted in the 4th
|
||||
;; cycle, and then deasserted on the latency cycle. So only one divide at
|
||||
;; a time, but the first/last 4 cycles can overlap.
|
||||
|
||||
;; ??? All divides block writes to hi/lo regs. hi/lo regs are written 4 cycles
|
||||
;; after the latency cycle for divides (e.g. 40/72). dmult writes lo in
|
||||
;; cycle 7, and hi in cycle 8. All other insns write hi/lo regs in cycle 7.
|
||||
;; Default for output dependencies is the difference in latencies, which is
|
||||
;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should
|
||||
;; stall for 33 cycles. This does not seem significant enough to worry about.
|
||||
|
||||
(define_insn_reservation "ir_sb1_divsi" 36
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "idiv")
|
||||
(eq_attr "mode" "SI")))
|
||||
"sb1_ex1, nothing*3, sb1_div*32")
|
||||
|
||||
(define_insn_reservation "ir_sb1_divdi" 68
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "idiv")
|
||||
(eq_attr "mode" "DI")))
|
||||
"sb1_ex1, nothing*3, sb1_div*64")
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpu_2pipes" 4
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt")
|
||||
(eq_attr "sb1_fp_pipes" "two")))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_fpu_1pipe" 4
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt")
|
||||
(eq_attr "sb1_fp_pipes" "one")))
|
||||
"sb1_fp1")
|
||||
|
||||
;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency
|
||||
;; otherwise.
|
||||
|
||||
;; ??? Blocks issue of another non-madd/msub after 4 cycles.
|
||||
|
||||
(define_insn_reservation "ir_sb1_fmadd_2pipes" 8
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fmadd")
|
||||
(eq_attr "sb1_fp_pipes" "two")))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_fmadd_1pipe" 8
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fmadd")
|
||||
(eq_attr "sb1_fp_pipes" "one")))
|
||||
"sb1_fp1")
|
||||
|
||||
(define_insn_reservation "ir_sb1_fcmp" 4
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(eq_attr "type" "fcmp"))
|
||||
"sb1_fp1")
|
||||
|
||||
;; mtc1 latency 5 cycles.
|
||||
|
||||
(define_insn_reservation "ir_sb1_mtxfer" 5
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "xfer")
|
||||
(match_operand 0 "fp_register_operand" "")))
|
||||
"sb1_fp0")
|
||||
|
||||
;; mfc1 latency 1 cycle.
|
||||
|
||||
(define_insn_reservation "ir_sb1_mfxfer" 1
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "xfer")
|
||||
(not (match_operand 0 "fp_register_operand" ""))))
|
||||
"sb1_fp0")
|
||||
|
||||
;; ??? Can deliver at most 1 result per every 6 cycles because of issue
|
||||
;; restrictions.
|
||||
|
||||
(define_insn_reservation "ir_sb1_divsf_2pipes" 24
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fdiv")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "two"))))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_divsf_1pipes" 24
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fdiv")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "one"))))
|
||||
"sb1_fp1")
|
||||
|
||||
;; ??? Can deliver at most 1 result per every 8 cycles because of issue
|
||||
;; restrictions.
|
||||
|
||||
(define_insn_reservation "ir_sb1_divdf_2pipes" 32
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fdiv")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "two"))))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_divdf_1pipe" 32
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fdiv")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "one"))))
|
||||
"sb1_fp1")
|
||||
|
||||
;; ??? Can deliver at most 1 result per every 7 cycles because of issue
|
||||
;; restrictions.
|
||||
|
||||
(define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "two"))))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "one"))))
|
||||
"sb1_fp1")
|
||||
|
||||
;; ??? Can deliver at most 1 result per every 10 cycles because of issue
|
||||
;; restrictions.
|
||||
|
||||
(define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(and (eq_attr "mode" "DF")
|
||||
(eq_attr "sb1_fp_pipes" "two"))))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "fsqrt")
|
||||
(and (eq_attr "mode" "DF")
|
||||
(eq_attr "sb1_fp_pipes" "one"))))
|
||||
"sb1_fp1")
|
||||
|
||||
;; ??? Can deliver at most 1 result per every 4 cycles because of issue
|
||||
;; restrictions.
|
||||
|
||||
(define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "two"))))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(and (eq_attr "mode" "SF")
|
||||
(eq_attr "sb1_fp_pipes" "one"))))
|
||||
"sb1_fp1")
|
||||
|
||||
;; ??? Can deliver at most 1 result per every 7 cycles because of issue
|
||||
;; restrictions.
|
||||
|
||||
(define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(and (eq_attr "mode" "DF")
|
||||
(eq_attr "sb1_fp_pipes" "two"))))
|
||||
"sb1_fp1 | sb1_fp0")
|
||||
|
||||
(define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28
|
||||
(and (eq_attr "cpu" "sb1")
|
||||
(and (eq_attr "type" "frsqrt")
|
||||
(and (eq_attr "mode" "DF")
|
||||
(eq_attr "sb1_fp_pipes" "one"))))
|
||||
"sb1_fp1")
|
||||
|
|
@ -482,7 +482,8 @@ in the following sections.
|
|||
-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
|
||||
-mfix-vr4120 -mno-fix-vr4120 -mfix-sb1 -mno-fix-sb1 @gol
|
||||
-mflush-func=@var{func} -mno-flush-func @gol
|
||||
-mbranch-likely -mno-branch-likely}
|
||||
-mbranch-likely -mno-branch-likely @gol
|
||||
-mfp-exceptions -mno-fp-exceptions}
|
||||
|
||||
@emph{i386 and x86-64 Options}
|
||||
@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
|
||||
|
|
@ -8178,6 +8179,17 @@ architecture. An exception is for the MIPS32 and MIPS64 architectures
|
|||
and processors which implement those architectures; for those, Branch
|
||||
Likely instructions will not be generated by default because the MIPS32
|
||||
and MIPS64 architectures specifically deprecate their use.
|
||||
|
||||
@item -mfp-exceptions
|
||||
@itemx -mno-fp-exceptions
|
||||
@opindex mfp-exceptions
|
||||
Specifies whether FP exceptions are enabled. This affects how we schedule
|
||||
FP instructions for some processors. The default is that FP exceptions are
|
||||
enabled.
|
||||
|
||||
For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
|
||||
64-bit code, then we can use both FP pipes. Otherwise, we can only use one
|
||||
FP pipe.
|
||||
@end table
|
||||
|
||||
@node i386 and x86-64 Options
|
||||
|
|
|
|||
Loading…
Reference in New Issue