[PATCH 5/17][ARM] Enable HI mode moves for floating point values.
gcc/ 2016-09-23 Jiong Wang <jiong.wang@arm.com> Matthew Wahab <matthew.wahab@arm.com> * config/arm/arm.c (output_move_vfp): Weaken assert to allow HImode. (arm_hard_regno_mode_ok): Allow HImode values in VFP registers. * config/arm/arm.md (*movhi_bytes): Disable when VFP registers are available. Also fix some white-space. * config/arm/vfp.md (*arm_movhi_vfp): New. (*thumb2_movhi_vfp): New. testsuite/ 2016-09-23 Matthew Wahab <matthew.wahab@arm.com> * gcc.target/arm/short-vfp-1.c: New. From-SVN: r240403
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Matthew Wahab
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@ -1,3 +1,14 @@
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2016-09-23 Jiong Wang <jiong.wang@arm.com>
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Matthew Wahab <matthew.wahab@arm.com>
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* config/arm/arm.c (output_move_vfp): Weaken assert to allow
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HImode.
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(arm_hard_regno_mode_ok): Allow HImode values in VFP registers.
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* config/arm/arm.md (*movhi_bytes): Disable when VFP registers are
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available. Also fix some white-space.
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* config/arm/vfp.md (*arm_movhi_vfp): New.
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(*thumb2_movhi_vfp): New.
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2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
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* config/arm/arm-c.c (arm_cpu_builtins): Define
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@ -18722,6 +18722,7 @@ output_move_vfp (rtx *operands)
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gcc_assert ((mode == HFmode && TARGET_HARD_FLOAT && TARGET_VFP)
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|| mode == SFmode
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|| mode == DFmode
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|| mode == HImode
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|| mode == SImode
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|| mode == DImode
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|| (TARGET_NEON && VALID_NEON_DREG_MODE (mode)));
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@ -23515,6 +23516,10 @@ arm_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
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if (mode == HFmode)
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return VFP_REGNO_OK_FOR_SINGLE (regno);
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/* VFP registers can hold HImode values. */
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if (mode == HImode)
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return VFP_REGNO_OK_FOR_SINGLE (regno);
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if (TARGET_NEON)
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return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
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|| (VALID_NEON_QREG_MODE (mode)
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@ -6700,7 +6700,7 @@
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[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r")
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(match_operand:HI 1 "general_operand" "rIk,K,n,r,mi"))]
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"TARGET_ARM
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&& arm_arch4
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&& arm_arch4 && !(TARGET_HARD_FLOAT && TARGET_VFP)
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&& (register_operand (operands[0], HImode)
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|| register_operand (operands[1], HImode))"
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"@
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@ -6726,7 +6726,7 @@
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(define_insn "*movhi_bytes"
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[(set (match_operand:HI 0 "s_register_operand" "=r,r,r")
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(match_operand:HI 1 "arm_rhs_operand" "I,rk,K"))]
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"TARGET_ARM"
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"TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_VFP)"
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"@
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mov%?\\t%0, %1\\t%@ movhi
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mov%?\\t%0, %1\\t%@ movhi
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@ -6734,7 +6734,7 @@
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[(set_attr "predicable" "yes")
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(set_attr "type" "mov_imm,mov_reg,mvn_imm")]
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)
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;; We use a DImode scratch because we may occasionally need an additional
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;; temporary if the address isn't offsettable -- push_reload doesn't seem
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;; to take any notice of the "o" constraints on reload_memory_operand operand.
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@ -18,6 +18,99 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>. */
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;; Patterns for HI moves which provide more data transfer instructions when VFP
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;; support is enabled.
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(define_insn "*arm_movhi_vfp"
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[(set
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(match_operand:HI 0 "nonimmediate_operand"
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"=rk, r, r, m, r, *t, r, *t")
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(match_operand:HI 1 "general_operand"
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"rIk, K, n, r, mi, r, *t, *t"))]
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"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
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&& (register_operand (operands[0], HImode)
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|| register_operand (operands[1], HImode))"
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{
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switch (which_alternative)
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{
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case 0:
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return "mov%?\t%0, %1\t%@ movhi";
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case 1:
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return "mvn%?\t%0, #%B1\t%@ movhi";
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case 2:
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return "movw%?\t%0, %L1\t%@ movhi";
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case 3:
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return "strh%?\t%1, %0\t%@ movhi";
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case 4:
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return "ldrh%?\t%0, %1\t%@ movhi";
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case 5:
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case 6:
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return "vmov%?\t%0, %1\t%@ int";
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case 7:
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return "vmov%?.f32\t%0, %1\t%@ int";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "predicable" "yes")
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(set_attr_alternative "type"
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[(if_then_else
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(match_operand 1 "const_int_operand" "")
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(const_string "mov_imm")
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(const_string "mov_reg"))
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(const_string "mvn_imm")
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(const_string "mov_imm")
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(const_string "store1")
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(const_string "load1")
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(const_string "f_mcr")
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(const_string "f_mrc")
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(const_string "fmov")])
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(set_attr "pool_range" "*, *, *, *, 256, *, *, *")
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(set_attr "neg_pool_range" "*, *, *, *, 244, *, *, *")
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(set_attr "length" "4")]
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)
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(define_insn "*thumb2_movhi_vfp"
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[(set
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(match_operand:HI 0 "nonimmediate_operand"
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"=rk, r, l, r, m, r, *t, r, *t")
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(match_operand:HI 1 "general_operand"
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"rk, I, Py, n, r, m, r, *t, *t"))]
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"TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP
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&& (register_operand (operands[0], HImode)
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|| register_operand (operands[1], HImode))"
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{
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switch (which_alternative)
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{
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case 0:
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case 1:
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case 2:
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return "mov%?\t%0, %1\t%@ movhi";
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case 3:
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return "movw%?\t%0, %L1\t%@ movhi";
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case 4:
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return "strh%?\t%1, %0\t%@ movhi";
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case 5:
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return "ldrh%?\t%0, %1\t%@ movhi";
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case 6:
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case 7:
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return "vmov%?\t%0, %1\t%@ int";
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case 8:
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return "vmov%?.f32\t%0, %1\t%@ int";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it"
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"yes, no, yes, no, no, no, no, no, no")
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(set_attr "type"
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"mov_reg, mov_imm, mov_imm, mov_imm, store1, load1,\
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f_mcr, f_mrc, fmov")
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(set_attr "pool_range" "*, *, *, *, *, 4094, *, *, *")
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(set_attr "neg_pool_range" "*, *, *, *, *, 250, *, *, *")
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(set_attr "length" "2, 4, 2, 4, 4, 4, 4, 4, 4")]
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)
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;; SImode moves
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;; ??? For now do not allow loading constants into vfp regs. This causes
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;; problems because small constants get converted into adds.
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@ -1,3 +1,7 @@
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2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
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* gcc.target/arm/short-vfp-1.c: New.
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2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
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* gcc.target/arm/attr-fp16-arith-1.c: New.
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45
gcc/testsuite/gcc.target/arm/short-vfp-1.c
Normal file
45
gcc/testsuite/gcc.target/arm/short-vfp-1.c
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@ -0,0 +1,45 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target arm_vfp_ok }
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/* { dg-options "-mfpu=vfp" } */
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int
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test_sisf (float x)
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{
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return (int)x;
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}
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short
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test_hisf (float x)
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{
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return (short)x;
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}
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float
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test_sfsi (int x)
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{
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return (float)x;
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}
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float
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test_sfhi (short x)
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{
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return (float)x;
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}
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short
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test_hisi (int x)
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{
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return (short)x;
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}
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int
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test_sihi (short x)
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{
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return (int)x;
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}
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/* {dg-final { scan-assembler-times {vcvt\.s32\.f32\ts[0-9]+,s[0-9]+} 2 }} */
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/* {dg-final { scan-assembler-times {vcvt\.f32\.s32\ts[0-9]+,s[0-9]+} 2 }} */
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/* {dg-final { scan-assembler-times {vmov\tr[0-9]+,s[0-9]+} 2 }} */
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/* {dg-final { scan-assembler-times {vmov\ts[0-9]+,r[0-9]+} 2 }} */
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/* {dg-final { scan-assembler-times {sxth\tr[0-9]+,r[0-9]+} 2 }} */
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