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divtab.c: Fix formatting and comments throughout the file.

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* config/sh/divtab.c: Fix formatting and comments throughout the file.
	* config/sh/sh4-300.md: Likewise.
	* config/sh/sh4a.md: Likewise.
	* config/sh/constraints.md: Likewise.
	* config/sh/sh.md: Likewise.
	* config/sh/netbsd-elf.h: Likewise.
	* config/sh/predicates.md: Likewise.
	* config/sh/sh-protos.h: Likewise.
	* config/sh/ushmedia.h: Likewise.
	* config/sh/linux.h: Likewise.
	* config/sh/sh.c: Likewise.
	* config/sh/superh.h: Likewise.
	* config/sh/elf.h: Likewise.
	* config/sh/sh4.md: Likewise.
	* config/sh/sh.h: Likewise.

From-SVN: r195703
This commit is contained in:
Oleg Endo 2013-02-03 20:06:01 +00:00
parent 1a04ac2bc8
commit 50fe8924df
16 changed files with 689 additions and 849 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
gcc/ChangeLog
View File

@ -1,3 +1,21 @@
2013-02-03 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/divtab.c: Fix formatting and comments throughout the file.
* config/sh/sh4-300.md: Likewise.
* config/sh/sh4a.md: Likewise.
* config/sh/constraints.md: Likewise.
* config/sh/sh.md: Likewise.
* config/sh/netbsd-elf.h: Likewise.
* config/sh/predicates.md: Likewise.
* config/sh/sh-protos.h: Likewise.
* config/sh/ushmedia.h: Likewise.
* config/sh/linux.h: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/superh.h: Likewise.
* config/sh/elf.h: Likewise.
* config/sh/sh4.md: Likewise.
* config/sh/sh.h: Likewise.
2013-02-03 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* config/pa/constraints.md: Adjust unused letters. Change "T"

4
gcc/config/sh/constraints.md
View File

@ -26,7 +26,7 @@
;; Csu: unsigned 16-bit constant, literal or symbolic
;; Csy: label or symbol
;; Cpg: non-explicit constants that can be directly loaded into a general
;; purpose register in PIC code. like 's' except we don't allow
;; purpose register in PIC code. Like 's' except we don't allow
;; PIC_ADDR_P
;; IJKLMNOP: CONT_INT constants
;; Ixx: signed xx bit
@ -315,7 +315,7 @@
(match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))")))
(define_memory_constraint "Sra"
"A memory reference that uses a simple register addressing."
"A memory reference that uses simple register addressing."
(and (match_test "MEM_P (op)")
(match_test "REG_P (XEXP (op, 0))")))

9
gcc/config/sh/divtab.c
View File

@ -53,7 +53,8 @@ double max_defect3 = 0.;
double max_defect3_x;
int max_defect3_val;
static double note_defect3 (int val, double d2, double y2d, double x)
static double
note_defect3 (int val, double d2, double y2d, double x)
{
int cutoff_val = val >> CUTOFF_BITS;
double cutoff;
@ -172,8 +173,10 @@ main ()
printf (" Min defect: %e at %e\n", min_defect, min_defect_x);
printf (" Max 2nd step defect: %e at %e\n", max_defect2, max_defect2_x);
printf (" Min 2nd step defect: %e at %e\n", min_defect2, min_defect2_x);
printf (" Max div defect: %e at %d:%e\n", max_defect3, max_defect3_val, max_defect3_x);
printf (" Min div defect: %e at %d:%e\n", min_defect3, min_defect3_val, min_defect3_x);
printf (" Max div defect: %e at %d:%e\n", max_defect3, max_defect3_val,
max_defect3_x);
printf (" Min div defect: %e at %d:%e\n", min_defect3, min_defect3_val,
min_defect3_x);
printf (" Defect at 1: %e\n",
calc_defect (1., constants[0], factors[0]));
printf (" Defect at -2: %e */\n",

7
gcc/config/sh/elf.h
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@ -22,17 +22,17 @@ along with GCC; see the file COPYING3. If not see
#undef TARGET_ELF
#define TARGET_ELF 1
/* Generate DWARF2 debugging information and make it the default */
/* Generate DWARF2 debugging information and make it the default. */
#define DWARF2_DEBUGGING_INFO 1
#undef PREFERRED_DEBUGGING_TYPE
#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
/* use a more compact format for line information */
/* Use a more compact format for line information. */
#define DWARF2_ASM_LINE_DEBUG_INFO 1
#undef WCHAR_TYPE
/* #define WCHAR_TYPE (TARGET_SH5 ? "int" : "long int") */
/* #define WCHAR_TYPE (TARGET_SH5 ? "int" : "long int") */
#define WCHAR_TYPE SH_ELF_WCHAR_TYPE
#undef WCHAR_TYPE_SIZE
@ -40,7 +40,6 @@ along with GCC; see the file COPYING3. If not see
/* The prefix to add to user-visible assembler symbols. */
#undef LOCAL_LABEL_PREFIX
#define LOCAL_LABEL_PREFIX "."

1
gcc/config/sh/linux.h
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@ -57,7 +57,6 @@ along with GCC; see the file COPYING3. If not see
%{static:-static}"
/* Output assembler code to STREAM to call the profiler. */
#undef FUNCTION_PROFILER
#define FUNCTION_PROFILER(STREAM,LABELNO) \
do { \

1
gcc/config/sh/netbsd-elf.h
View File

@ -41,7 +41,6 @@ along with GCC; see the file COPYING3. If not see
NetBSD ELF LINK_SPEC. */
/* LINK_EMUL_PREFIX from sh/elf.h */
#undef SUBTARGET_LINK_EMUL_SUFFIX
#define SUBTARGET_LINK_EMUL_SUFFIX "_nbsd"

176
gcc/config/sh/predicates.md
View File

@ -18,7 +18,6 @@
;; <http://www.gnu.org/licenses/>.
;; TODO: Add a comment here.
(define_predicate "trapping_target_operand"
(match_code "if_then_else")
{
@ -58,8 +57,7 @@
&& INTVAL (XEXP (cond, 1)) == 3);
})
;; TODO: Add a comment here.
;; A logical operand that can be used in an shmedia and insn.
(define_predicate "and_operand"
(match_code "subreg,reg,const_int")
{
@ -77,7 +75,6 @@
;; Like arith_reg_dest, but this predicate is defined with
;; define_special_predicate, not define_predicate.
(define_special_predicate "any_arith_reg_dest"
(match_code "subreg,reg")
{
@ -86,7 +83,6 @@
;; Like register_operand, but this predicate is defined with
;; define_special_predicate, not define_predicate.
(define_special_predicate "any_register_operand"
(match_code "subreg,reg")
{
@ -94,7 +90,6 @@
})
;; Returns 1 if OP is a valid source operand for an arithmetic insn.
(define_predicate "arith_operand"
(match_code "subreg,reg,const_int,truncate")
{
@ -132,7 +127,6 @@
;; Like above, but for DImode destinations: forbid paradoxical DImode
;; subregs, because this would lead to missing sign extensions when
;; truncating from DImode to SImode.
(define_predicate "arith_reg_dest"
(match_code "subreg,reg")
{
@ -144,7 +138,6 @@
})
;; Returns 1 if OP is a normal arithmetic register.
(define_predicate "arith_reg_operand"
(match_code "subreg,reg,sign_extend")
{
@ -190,7 +183,6 @@
})
;; Returns 1 if OP is a valid source operand for a compare insn.
(define_predicate "arith_reg_or_0_operand"
(match_code "subreg,reg,const_int,const_vector")
{
@ -203,21 +195,18 @@
return 0;
})
;; TODO: Add a comment here.
;; Returns 1 if OP is a floating point operator with two operands.
(define_predicate "binary_float_operator"
(and (match_code "plus,minus,mult,div")
(match_test "GET_MODE (op) == mode")))
;; TODO: Add a comment here.
;; Returns 1 if OP is a logical operator with two operands.
(define_predicate "binary_logical_operator"
(and (match_code "and,ior,xor")
(match_test "GET_MODE (op) == mode")))
;; Return 1 of OP is an address suitable for a cache manipulation operation.
;; Return 1 if OP is an address suitable for a cache manipulation operation.
;; MODE has the meaning as in address_operand.
(define_special_predicate "cache_address_operand"
(match_code "plus,reg")
{
@ -234,8 +223,7 @@
return address_operand (op, mode);
})
;; Return 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
(define_predicate "cmp_operand"
(match_code "subreg,reg,const_int")
{
@ -248,8 +236,8 @@
return arith_reg_operand (op, mode);
})
;; TODO: Add a comment here.
;; Returns true if OP is an operand that can be used as the first operand in
;; the cstoresi4 expander pattern.
(define_predicate "cmpsi_operand"
(match_code "subreg,reg,const_int")
{
@ -260,19 +248,18 @@
return arith_operand (op, mode);
})
;; TODO: Add a comment here.
(define_predicate "commutative_float_operator"
(and (match_code "plus,mult")
(match_test "GET_MODE (op) == mode")))
;; TODO: Add a comment here.
;; Returns true if OP is a comutative float operator.
;; This predicate is currently unused.
;;(define_predicate "commutative_float_operator"
;; (and (match_code "plus,mult")
;; (match_test "GET_MODE (op) == mode")))
;; Returns true if OP is a equal or not equal operator.
(define_predicate "equality_comparison_operator"
(match_code "eq,ne"))
;; TODO: Add a comment here.
;; Returns true if OP is an arithmetic operand that is zero extended during
;; an operation.
(define_predicate "extend_reg_operand"
(match_code "subreg,reg,truncate")
{
@ -281,8 +268,7 @@
: arith_reg_operand) (op, mode);
})
;; TODO: Add a comment here.
;; Like extend_reg_operand, but also allow a constant 0.
(define_predicate "extend_reg_or_0_operand"
(match_code "subreg,reg,truncate,const_int")
{
@ -292,15 +278,14 @@
})
;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
(define_predicate "ext_dest_operand"
(match_code "subreg,reg")
{
return arith_reg_operand (op, mode);
})
;; TODO: Add a comment here.
;; Returns true if OP can be used as a destination register for shmedia floating
;; point to integer conversions.
(define_predicate "fp_arith_reg_dest"
(match_code "subreg,reg")
{
@ -310,8 +295,8 @@
return fp_arith_reg_operand (op, mode);
})
;; TODO: Add a comment here.
;; Returns true if OP is a floating point register that can be used in floating
;; point arithmetic operations.
(define_predicate "fp_arith_reg_operand"
(match_code "subreg,reg")
{
@ -332,8 +317,7 @@
return 0;
})
;; TODO: Add a comment here.
;; Returns true if OP is the FPSCR.
(define_predicate "fpscr_operand"
(match_code "reg")
{
@ -382,8 +366,7 @@
(and (match_code "const_double")
(match_test "op == sh_fsca_int2sf ()")))
;; TODO: Add a comment here.
;; Returns true if OP is an operand that is zero extended during an operation.
(define_predicate "general_extend_operand"
(match_code "subreg,reg,mem,truncate")
{
@ -423,9 +406,9 @@
;; Returns 1 if OP can be source of a simple move operation. Same as
;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
;; are subregs of system registers.
(define_predicate "general_movsrc_operand"
(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,const,const_vector")
(match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,
const,const_vector")
{
if (t_reg_operand (op, mode))
return 0;
@ -482,7 +465,6 @@
})
;; Returns 1 if OP is a MEM that does not use displacement addressing.
(define_predicate "movsrc_no_disp_mem_operand"
(match_code "mem")
{
@ -491,7 +473,6 @@
;; Returns 1 if OP can be a destination of a move. Same as
;; general_operand, but no preinc allowed.
(define_predicate "general_movdst_operand"
(match_code "subreg,reg,mem")
{
@ -534,7 +515,6 @@
})
;; Returns 1 if OP is a POST_INC on stack pointer register.
(define_predicate "sh_no_delay_pop_operand"
(match_code "mem")
{
@ -551,7 +531,6 @@
})
;; Returns 1 if OP is a MEM that can be source of a simple move operation.
(define_predicate "unaligned_load_operand"
(match_code "mem")
{
@ -599,13 +578,12 @@
&& sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
})
;; TODO: Add a comment here.
;; Returns true if OP is some kind of greater comparision.
(define_predicate "greater_comparison_operator"
(match_code "gt,ge,gtu,geu"))
;; TODO: Add a comment here.
;; Returns true if OP is an operand suitable for shmedia reload_inqi and
;; reload_inhi insns.
(define_predicate "inqhi_operand"
(match_code "truncate")
{
@ -617,28 +595,26 @@
return REG_P (op) && FP_REGISTER_P (REGNO (op));
})
;; TODO: Add a comment here.
(define_special_predicate "int_gpr_dest"
(match_code "subreg,reg")
{
enum machine_mode op_mode = GET_MODE (op);
if (GET_MODE_CLASS (op_mode) != MODE_INT
|| GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
return 0;
if (! reload_completed)
return 0;
return true_regnum (op) <= LAST_GENERAL_REG;
})
;; TODO: Add a comment here.
;; Returns true if OP is a general purpose integer register.
;; This predicate is currently unused.
;;(define_special_predicate "int_gpr_dest"
;; (match_code "subreg,reg")
;;{
;; enum machine_mode op_mode = GET_MODE (op);
;;
;; if (GET_MODE_CLASS (op_mode) != MODE_INT
;; || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
;; return 0;
;; if (! reload_completed)
;; return 0;
;; return true_regnum (op) <= LAST_GENERAL_REG;
;;})
;; Returns true if OP is some kind of less comparison.
(define_predicate "less_comparison_operator"
(match_code "lt,le,ltu,leu"))
;; Returns 1 if OP is a valid source operand for a logical operation.
(define_predicate "logical_operand"
(match_code "subreg,reg,const_int")
{
@ -678,14 +654,12 @@
return 0;
})
;; TODO: Add a comment here.
;; Returns true if OP is a logical operator.
(define_predicate "logical_operator"
(match_code "and,ior,xor"))
;; Like arith_reg_operand, but for register source operands of narrow
;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
(define_predicate "logical_reg_operand"
(match_code "subreg,reg")
{
@ -697,8 +671,7 @@
return arith_reg_operand (op, mode);
})
;; TODO: Add a comment here.
;; Returns true if OP is a valid bit offset value for the shmedia mextr insns.
(define_predicate "mextr_bit_offset"
(match_code "const_int")
{
@ -710,19 +683,19 @@
return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
})
;; TODO: Add a comment here.
;; Returns true if OP is a constant -1, 0 or an zero extended register that
;; can be used as an operator in the *subsi3_media insn.
(define_predicate "minuend_operand"
(match_code "subreg,reg,truncate,const_int")
{
return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
})
;; TODO: Add a comment here.
(define_predicate "noncommutative_float_operator"
(and (match_code "minus,div")
(match_test "GET_MODE (op) == mode")))
;; Returns true if OP is a noncommutative floating point operator.
;; This predicate is currently unused.
;;(define_predicate "noncommutative_float_operator"
;; (and (match_code "minus,div")
;; (match_test "GET_MODE (op) == mode")))
;; UNORDERED is only supported on SHMEDIA.
@ -735,8 +708,7 @@
(ior (match_operand 0 "equality_comparison_operator")
(match_operand 0 "greater_comparison_operator")))
;; TODO: Add a comment here.
;; Returns true if OP is a constant vector.
(define_predicate "sh_const_vec"
(match_code "const_vector")
{
@ -755,7 +727,6 @@
;; Determine if OP is a constant vector matching MODE with only one
;; element that is not a sign extension. Two byte-sized elements
;; count as one.
(define_predicate "sh_1el_vec"
(match_code "const_vector")
{
@ -789,7 +760,6 @@
;; Like register_operand, but take into account that SHMEDIA can use
;; the constant zero like a general register.
(define_predicate "sh_register_operand"
(match_code "reg,subreg,const_int,const_double")
{
@ -798,8 +768,8 @@
return register_operand (op, mode);
})
;; TODO: Add a comment here.
;; Returns true if OP is a vector which is composed of one element that is
;; repeated.
(define_predicate "sh_rep_vec"
(match_code "const_vector,parallel")
{
@ -826,10 +796,10 @@
return 1;
})
;; TODO: Add a comment here.
;; Returns true if OP is a valid shift count operand for shift operations.
(define_predicate "shift_count_operand"
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,zero_extend,sign_extend")
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,
zero_extend,sign_extend")
{
/* Allow T_REG as shift count for dynamic shifts, although it is not
really possible. It will then be copied to a general purpose reg. */
@ -844,8 +814,8 @@
: shift_count_reg_operand (op, mode));
})
;; TODO: Add a comment here.
;; Returns true if OP is a valid shift count operand in a register which can
;; be used by shmedia shift insns.
(define_predicate "shift_count_reg_operand"
(match_code "subreg,reg,zero_extend,sign_extend")
{
@ -890,19 +860,16 @@
(ior (match_test "! satisfies_constraint_P27 (op)")
(match_test "satisfies_constraint_M (op)"))))
;; TODO: Add a comment here.
;; Returns true if OP is some kind of a shift operator.
(define_predicate "shift_operator"
(match_code "ashift,ashiftrt,lshiftrt"))
;; TODO: Add a comment here.
;; Returns true if OP is a symbol reference.
(define_predicate "symbol_ref_operand"
(match_code "symbol_ref"))
;; Same as target_reg_operand, except that label_refs and symbol_refs
;; are accepted before reload.
(define_special_predicate "target_operand"
(match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
{
@ -916,8 +883,7 @@
return target_reg_operand (op, mode);
})
;; Accept pseudos and branch target registers.
;; A predicate that accepts pseudos and branch target registers.
(define_special_predicate "target_reg_operand"
(match_code "subreg,reg")
{
@ -942,8 +908,7 @@
return 0;
})
;; TODO: Add a comment here.
;; Returns true if OP is a valid operand for the shmedia mperm.w insn.
(define_special_predicate "trunc_hi_operand"
(match_code "subreg,reg,truncate")
{
@ -955,8 +920,8 @@
return extend_reg_operand (op, mode);
})
;; Return 1 of OP is an address suitable for an unaligned access instruction.
;; Returns true if OP is an address suitable for an unaligned access
;; instruction.
(define_special_predicate "ua_address_operand"
(match_code "subreg,reg,plus")
{
@ -966,22 +931,19 @@
return address_operand (op, QImode);
})
;; TODO: Add a comment here.
;; Returns true if OP is a valid offset for an unaligned memory address.
(define_predicate "ua_offset"
(match_code "const_int")
{
return satisfies_constraint_I06 (op);
})
;; TODO: Add a comment here.
;; Returns true if OP is a floating point operator with one operand.
(define_predicate "unary_float_operator"
(and (match_code "abs,neg,sqrt")
(match_test "GET_MODE (op) == mode")))
;; Return 1 if OP is a valid source operand for xor.
(define_predicate "xor_operand"
(match_code "subreg,reg,const_int")
{
@ -1080,7 +1042,7 @@
return sh_eval_treg_value (op) >= 0;
})
;; Returns true of OP is arith_reg_operand or t_reg_operand.
;; Returns true if OP is arith_reg_operand or t_reg_operand.
(define_predicate "arith_reg_or_t_reg_operand"
(ior (match_operand 0 "arith_reg_operand")
(match_operand 0 "t_reg_operand")))
@ -1124,7 +1086,7 @@
})
;; A predicate that determines whether a given constant is a valid
;; displacement for a gbr load/store of the specified mode.
;; displacement for a GBR load/store of the specified mode.
(define_predicate "gbr_displacement"
(match_code "const_int")
{

3
gcc/config/sh/sh-protos.h
View File

@ -212,7 +212,8 @@ extern void sh_pr_nosave_low_regs (struct cpp_reader *);
extern rtx function_symbol (rtx, const char *, enum sh_function_kind);
extern rtx sh_get_pr_initial_val (void);
extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, signed int, enum machine_mode);
extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
signed int, enum machine_mode);
extern rtx sh_dwarf_register_span (rtx);
extern rtx replace_n_hard_rtx (rtx, rtx *, int , int);

494
gcc/config/sh/sh.c
View File

File diff suppressed because it is too large Load Diff

203
gcc/config/sh/sh.h
View File

@ -129,35 +129,35 @@ extern int code_for_indirect_jump_scratch;
#define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
#define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
#define SELECT_SH1 (MASK_SH1)
#define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
#define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
#define SELECT_SH1 (MASK_SH1)
#define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
#define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
| MASK_FPU_SINGLE)
#define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
#define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
| MASK_HARD_SH2A_DOUBLE \
| MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
#define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
| MASK_SH1 | MASK_FPU_SINGLE)
#define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
#define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
| MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
| MASK_SH2 | MASK_SH1)
#define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
#define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
#define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
#define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
#define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
#define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
#define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
#define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
#define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
#define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
| SELECT_SH3)
#define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
#define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
#define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
#define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
#define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
#define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
#define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
#define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
#define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
#define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
#define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
#define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
#if SUPPORT_SH1
@ -404,7 +404,6 @@ extern enum sh_divide_strategy_e sh_div_strategy;
/* Define this if most significant bit is lowest numbered
in instructions that operate on numbered bit-fields. */
#define BITS_BIG_ENDIAN 0
/* Define this if most significant byte of a word is the lowest numbered. */
@ -537,15 +536,15 @@ extern enum sh_divide_strategy_e sh_div_strategy;
/* Register allocation for the Renesas calling convention:
r0 arg return
r1..r3 scratch
r0 arg return
r1..r3 scratch
r4..r7 args in
r8..r13 call saved
r14 frame pointer/call saved
r15 stack pointer
ap arg pointer (doesn't really exist, always eliminated)
pr subroutine return address
t t bit
t t bit
mach multiply/accumulate result, high part
macl multiply/accumulate result, low part.
fpul fp/int communication register
@ -559,7 +558,7 @@ extern enum sh_divide_strategy_e sh_div_strategy;
extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
#define SH_REGISTER_NAMES_INITIALIZER \
{ \
{ \
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
@ -661,12 +660,11 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
#define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
/* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
#define FIRST_BANKED_REG R0_REG
#define LAST_BANKED_REG R7_REG
#define BANKED_REGISTER_P(REGNO) \
IN_RANGE ((REGNO), \
#define BANKED_REGISTER_P(REGNO) \
IN_RANGE ((REGNO), \
(unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
(unsigned HOST_WIDE_INT) LAST_BANKED_REG)
@ -676,7 +674,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
(unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
#define GENERAL_OR_AP_REGISTER_P(REGNO) \
(GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
(GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
|| ((REGNO) == FRAME_POINTER_REGNUM))
#define FP_REGISTER_P(REGNO) \
@ -730,9 +728,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
Mach register is fixed 'cause it's only 10 bits wide for SH1.
It is 32 bits wide for SH2. */
#define FIXED_REGISTERS \
{ \
#define FIXED_REGISTERS \
{ \
/* Regular registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 1, \
@ -770,9 +767,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
The latter must include the registers where values are returned
and the register where structure-value addresses are passed.
Aside from that, you can include as many other registers as you like. */
#define CALL_USED_REGISTERS \
{ \
#define CALL_USED_REGISTERS \
{ \
/* Regular registers. */ \
1, 1, 1, 1, 1, 1, 1, 1, \
/* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
@ -817,7 +813,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
(TARGET_SHMEDIA32 \
&& GET_MODE_SIZE (MODE) > 4 \
&& (((REGNO) >= FIRST_GENERAL_REG + 10 \
&& (REGNO) <= FIRST_GENERAL_REG + 15) \
&& (REGNO) <= FIRST_GENERAL_REG + 15) \
|| TARGET_REGISTER_P (REGNO) \
|| (REGNO) == PR_MEDIA_REG))
@ -827,7 +823,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
but can be less for certain modes in special long registers.
On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
(XD_REGISTER_P (REGNO) \
? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
@ -836,8 +831,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
sh_hard_regno_mode_ok ((REGNO), (MODE))
/* Value is 1 if it is a good idea to tie two pseudo registers
@ -847,7 +841,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
That's the case for xd registers: we don't hold SFmode values in
them, so we can't tie an SFmode pseudos with one in another
floating-point mode. */
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \
|| (TARGET_SHMEDIA \
@ -860,7 +853,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
/* A C expression that is nonzero if hard register NEW_REG can be
considered for use as a rename register for OLD_REG register */
#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
@ -896,14 +888,14 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
pointer register. Secondly, the argument pointer register can always be
eliminated; it is replaced with either the stack or frame pointer.
Third, there is the return address pointer, which can also be replaced
with either the stack or the frame pointer. */
with either the stack or the frame pointer.
/* This is an array of structures. Each structure initializes one pair
This is an array of structures. Each structure initializes one pair
of eliminable registers. The "from" register number is given first,
followed by "to". Eliminations of the same "from" register are listed
in order of preference. */
in order of preference.
/* If you add any registers here that are not actually hard registers,
If you add any registers here that are not actually hard registers,
and that have any alternative of elimination that doesn't always
apply, you need to amend calc_live_regs to exclude it, because
reload spills all eliminable registers where it sees an
@ -911,7 +903,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
If you add any hard registers that can be eliminated in different
ways, you have to patch reload to spill them only when all alternatives
of elimination fail. */
#define ELIMINABLE_REGS \
{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
@ -923,7 +914,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
/* Define the offset between two registers, one to be eliminated, and the other
its replacement, at the start of a routine. */
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
OFFSET = initial_elimination_offset ((FROM), (TO))
@ -936,7 +926,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
/* Don't default to pcc-struct-return, because we have already specified
exactly how to return structures in the TARGET_RETURN_IN_MEMORY
target hook. */
#define DEFAULT_PCC_STRUCT_RETURN 0
#define SHMEDIA_REGS_STACK_ADJUST() \
@ -964,13 +953,14 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
in a smaller-numbered class.
For any two classes, it is very desirable that there be another
class that represents their union. */
class that represents their union.
/* The SH has two sorts of general registers, R0 and the rest. R0 can
The SH has two sorts of general registers, R0 and the rest. R0 can
be used as the destination of some of the arithmetic ops. There are
also some special purpose registers; the T bit register, the
Procedure Return Register and the Multiply Accumulate Registers. */
/* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
Procedure Return Register and the Multiply Accumulate Registers.
Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
reg_class_subunion. We don't want to have an actual union class
of these, because it would only be used when both classes are calculated
to give the same cost, but there is only one FPUL register.
@ -978,7 +968,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
applying to the actual instruction alternative considered. E.g., the
y/r alternative of movsi_ie is considered to have no more cost that
the r/r alternative, which is patently untrue. */
enum reg_class
{
NO_REGS,
@ -1030,7 +1019,6 @@ enum reg_class
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
#define REG_CLASS_CONTENTS \
{ \
/* NO_REGS: */ \
@ -1055,7 +1043,7 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
/* FP_REGS: */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
/* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
/* DF_HI_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
/* DF_REGS: */ \
{ 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
@ -1075,7 +1063,6 @@ enum reg_class
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
@ -1155,23 +1142,22 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* If defined, gives a class of registers that cannot be used as the
operand of a SUBREG that changes the mode of the object illegally. */
/* ??? We need to renumber the internal numbers for the frnn registers
operand of a SUBREG that changes the mode of the object illegally.
??? We need to renumber the internal numbers for the frnn registers
when in little endian in order to allow mode size changes. */
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
sh_cannot_change_mode_class (FROM, TO, CLASS)
/* Stack layout; function entry, exit and calling. */
/* Define the number of registers that can hold parameters.
These macros are used only in other macro definitions below. */
#define NPARM_REGS(MODE) \
(TARGET_FPU_ANY && (MODE) == SFmode \
? (TARGET_SH5 ? 12 : 8) \
: (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
: (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
&& (GET_MODE_CLASS (MODE) == MODE_FLOAT \
|| GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
? (TARGET_SH5 ? 12 : 8) \
: (TARGET_SH5 ? 8 : 4))
@ -1215,9 +1201,9 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
/* Some subroutine macros specific to this machine. */
#define BASE_RETURN_VALUE_REG(MODE) \
((TARGET_FPU_ANY && ((MODE) == SFmode)) \
((TARGET_FPU_ANY && ((MODE) == SFmode)) \
? FIRST_FP_RET_REG \
: TARGET_FPU_ANY && (MODE) == SCmode \
: TARGET_FPU_ANY && (MODE) == SCmode \
? FIRST_FP_RET_REG \
: (TARGET_FPU_DOUBLE \
&& ((MODE) == DFmode || (MODE) == SFmode \
@ -1239,7 +1225,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define FUNCTION_ARG_REGNO_P(REGNO) \
(((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
&& (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
|| (TARGET_FPU_ANY \
|| (TARGET_FPU_ANY \
&& (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
&& (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
+ NPARM_REGS (SFmode))))
@ -1254,7 +1240,6 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
of arguments scanned so far (including the invisible argument,
if any, which holds the structure-value-address).
Thus NARGREGS or more means all following args should go on the stack. */
enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
struct sh_args {
int arg_count[2];
@ -1380,14 +1365,14 @@ struct sh_args {
The SH doesn't care about double alignment, so we only
round doubles to even regs when asked to explicitly. */
#define ROUND_REG(CUM, MODE) \
(((TARGET_ALIGN_DOUBLE \
|| ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
&& (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
&& GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
+ ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
(((TARGET_ALIGN_DOUBLE \
|| ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
&& ((MODE) == DFmode || (MODE) == DCmode) \
&& (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE))) \
&& GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
+ ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
: (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
/* Initialize a variable CUM of type CUMULATIVE_ARGS
@ -1398,16 +1383,15 @@ struct sh_args {
the same reg for a given argument class.
For TARGET_HITACHI, the structure value pointer is passed in memory. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
(N_NAMED_ARGS), VOIDmode)
#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
/* Return boolean indicating arg of mode MODE will be passed in a reg.
This macro is only used in this file. */
#define PASS_IN_REG_P(CUM, MODE, TYPE) \
(((TYPE) == 0 \
|| (! TREE_ADDRESSABLE ((TYPE)) \
@ -1441,7 +1425,7 @@ struct sh_args {
foo (double); a: fr5,fr4
foo (float a, float b); a: fr5 b: fr4
foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
this should be the other way round...
this should be the other way round...
foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
#define FUNCTION_ARG_SCmode_WART 1
@ -1524,7 +1508,6 @@ struct sh_args {
We use two .aligns, so as to make sure that both the .long is aligned
on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
from the trapa instruction. */
#define FUNCTION_PROFILER(STREAM,LABELNO) \
{ \
if (TARGET_SHMEDIA) \
@ -1545,22 +1528,20 @@ struct sh_args {
/* Define this macro if the code for function profiling should come
before the function prologue. Normally, the profiling code comes
after. */
#define PROFILE_BEFORE_PROLOGUE
/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
the stack pointer does not matter. The value is tested only in
functions that have frame pointers.
No definition is equivalent to always zero. */
#define EXIT_IGNORE_STACK 1
/*
On the SH, the trampoline looks like
2 0002 D202 mov.l l2,r2
1 0000 D301 mov.l l1,r3
3 0004 422B jmp @r2
4 0006 0009 nop
2 0002 D202 mov.l l2,r2
1 0000 D301 mov.l l1,r3
3 0004 422B jmp @r2
4 0006 0009 nop
5 0008 00000000 l1: .long area
6 000c 00000000 l2: .long function */
@ -1577,7 +1558,6 @@ struct sh_args {
address for the frame COUNT steps up from the current frame.
FRAMEADDR is already the frame pointer of the COUNT frame, so we
can ignore COUNT. */
#define RETURN_ADDR_RTX(COUNT, FRAME) \
(((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
@ -1594,11 +1574,11 @@ struct sh_args {
#define HAVE_PRE_DECREMENT TARGET_SH1
#define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
? 0 : TARGET_SH1)
? 0 : TARGET_SH1)
#define USE_LOAD_PRE_DECREMENT(mode) 0
#define USE_STORE_POST_INCREMENT(mode) 0
#define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
? 0 : TARGET_SH1)
? 0 : TARGET_SH1)
#define MOVE_BY_PIECES_P(SIZE, ALIGN) \
(move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
@ -1618,7 +1598,6 @@ struct sh_args {
Since they use reg_renumber, they are safe only once reg_renumber
has been allocated, which happens in reginfo.c during register
allocation. */
#define REGNO_OK_FOR_BASE_P(REGNO) \
(GENERAL_OR_AP_REGISTER_P (REGNO) \
|| GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
@ -1630,11 +1609,9 @@ struct sh_args {
/* Maximum number of registers that can appear in a valid memory
address. */
#define MAX_REGS_PER_ADDRESS 2
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
@ -1661,7 +1638,7 @@ struct sh_args {
/* Macros for extra constraints. */
#define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
#define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
((GET_CODE ((OP)) == LABEL_REF) \
|| (GET_CODE ((OP)) == CONST \
&& GET_CODE (XEXP ((OP), 0)) == PLUS \
@ -1670,7 +1647,7 @@ struct sh_args {
#define IS_NON_EXPLICIT_CONSTANT_P(OP) \
(CONSTANT_P (OP) \
&& !CONST_INT_P (OP) \
&& !CONST_INT_P (OP) \
&& GET_CODE (OP) != CONST_DOUBLE \
&& (!flag_pic \
|| (LEGITIMATE_PIC_OPERAND_P (OP) \
@ -1699,7 +1676,7 @@ struct sh_args {
(GET_CODE (OP) == CONST \
&& (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
|| (GET_CODE (XEXP ((OP), 0)) == PLUS \
&& UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
&& UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
&& CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
#define PIC_ADDR_P(OP) \
@ -1766,7 +1743,6 @@ struct sh_args {
/* A C compound statement that attempts to replace X, which is an address
that needs reloading, with a valid memory address for an operand of
mode MODE. WIN is a C statement label elsewhere in the code. */
#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
do { \
if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
@ -1796,7 +1772,8 @@ struct sh_args {
/* Since the SH2e has only `float' support, it is desirable to make all
floating point types equivalent to `float'. */
#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE)\
? 32 : 64)
/* 'char' is signed by default. */
#define DEFAULT_SIGNED_CHAR 1
@ -1831,9 +1808,9 @@ struct sh_args {
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
be the code that says which one of the two operations is implicitly
done, UNKNOWN if none. */
/* For SHmedia, we can truncate to QImode easier using zero extension. */
/* FP registers can load SImode values, but don't implicitly sign-extend
done, UNKNOWN if none.
For SHmedia, we can truncate to QImode easier using zero extension.
FP registers can load SImode values, but don't implicitly sign-extend
them to DImode. */
#define LOAD_EXTEND_OP(MODE) \
(((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
@ -1901,14 +1878,14 @@ struct sh_args {
in particular. */
#define INSN_SETS_ARE_DELAYED(X) \
((NONJUMP_INSN_P (X) \
((NONJUMP_INSN_P (X) \
&& GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \
&& get_attr_is_sfunc (X)))
#define INSN_REFERENCES_ARE_DELAYED(X) \
((NONJUMP_INSN_P (X) \
((NONJUMP_INSN_P (X) \
&& GET_CODE (PATTERN (X)) != SEQUENCE \
&& GET_CODE (PATTERN (X)) != USE \
&& GET_CODE (PATTERN (X)) != CLOBBER \
@ -1936,7 +1913,6 @@ struct sh_args {
/* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
uses this information. Hence, the general register <-> floating point
register information here is not used for SFmode. */
#define REGCLASS_HAS_GENERAL_REG(CLASS) \
((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
|| (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
@ -1966,9 +1942,10 @@ struct sh_args {
#define SET_ASM_OP "\t.set\t"
/* How to change between sections. */
#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
#define DATA_SECTION_ASM_OP "\t.data"
#define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 \
? "\t.section\t.text..SHmedia32,\"ax\"" \
: "\t.text")
#define DATA_SECTION_ASM_OP "\t.data"
#if defined CRT_BEGIN || defined CRT_END
/* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
@ -2060,7 +2037,7 @@ struct sh_args {
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
: ((int) (REGNO) >= FIRST_FP_REG \
: ((int) (REGNO) >= FIRST_FP_REG \
&& ((int) (REGNO) \
<= (FIRST_FP_REG + \
((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
@ -2110,11 +2087,10 @@ struct sh_args {
/* Globalizing directive for a label. */
#define GLOBAL_ASM_OP "\t.global\t"
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
/* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
/* Output a relative address table. */
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
switch (GET_MODE (BODY)) \
{ \
case SImode: \
@ -2149,7 +2125,6 @@ struct sh_args {
}
/* Output an absolute table element. */
#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
if (! optimize || TARGET_BIGTABLE) \
asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
@ -2167,7 +2142,6 @@ struct sh_args {
The contents of this vector are what will be used to convert the insn
template into assembler code, so you can change the assembler output
by changing the contents of the vector. */
#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
@ -2177,7 +2151,6 @@ extern rtx sh_compare_op1;
/* Which processor to schedule for. The elements of the enumeration must
match exactly the cpu attribute in the sh.md file. */
enum processor_type {
PROCESSOR_SH1,
PROCESSOR_SH2,
@ -2216,14 +2189,12 @@ extern tree sh_deferred_function_attributes;
extern tree *sh_deferred_function_attributes_tail;
/* Set when processing a function with interrupt attribute. */
extern int current_function_interrupt;
/* Instructions with unfilled delay slots take up an
extra two bytes for the nop in the delay slot.
sh-dsp parallel processing insns are four bytes long. */
#define ADJUST_INSN_LENGTH(X, LENGTH) \
(LENGTH) += sh_insn_length_adjustment (X);
@ -2266,8 +2237,8 @@ extern int current_function_interrupt;
#define MODE_EXIT(ENTITY) \
(sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
#define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
&& (REGNO) == FPSCR_REG)
#define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
&& (REGNO) == FPSCR_REG)
#define MODE_NEEDED(ENTITY, INSN) \
(recog_memoized (INSN) >= 0 \
@ -2277,8 +2248,8 @@ extern int current_function_interrupt;
#define MODE_AFTER(ENTITY, MODE, INSN) \
(TARGET_HITACHI \
&& recog_memoized (INSN) >= 0 \
&& get_attr_fp_set (INSN) != FP_SET_NONE \
? (int) get_attr_fp_set (INSN) \
&& get_attr_fp_set (INSN) != FP_SET_NONE \
? (int) get_attr_fp_set (INSN) \
: (MODE))
#define MODE_PRIORITY_TO_MODE(ENTITY, N) \

546
gcc/config/sh/sh.md
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File diff suppressed because it is too large Load Diff

16
gcc/config/sh/sh4-300.md
View File

@ -35,26 +35,21 @@
;; Since SH4 is a dual issue machine,it is as if there are two
;; units so that any insn can be processed by either one
;; of the decoding unit.
(define_cpu_unit "sh4_300_pipe_01,sh4_300_pipe_02" "sh4_300_inst_pipeline")
;; The floating point units.
(define_cpu_unit "sh4_300_fpt,sh4_300_fpu,sh4_300_fds" "sh4_300_fpu_pipe")
;; integer multiplier unit
(define_cpu_unit "sh4_300_mul" "sh4_300_inst_pipeline")
;; LS unit
(define_cpu_unit "sh4_300_ls" "sh4_300_inst_pipeline")
;; The address calculator used for branch instructions.
;; This will be reserved after "issue" of branch instructions
;; and this is to make sure that no two branch instructions
;; can be issued in parallel.
(define_cpu_unit "sh4_300_br" "sh4_300_inst_pipeline")
;; ----------------------------------------------------
@ -85,7 +80,6 @@
"sh4_300_issue+sh4_300_mul")
;; Instructions without specific resource requirements with latency 1.
(define_insn_reservation "sh4_300_simple_arith" 1
(and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "mt_group,arith,dyn_shift,prset"))
@ -153,7 +147,6 @@
;; or likely and likely not predicted, we might want to fill the delay slot.
;; However, there appears to be no machinery to make the compiler
;; recognize these scenarios.
(define_insn_reservation "sh4_300_branch" 1
(and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "cbranch,jump,return,jump_ind"))
@ -169,8 +162,11 @@
;; Group: CO
;; Latency: 1-5
;; Issue Rate: 1
;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
;; cwb is used for the sequence
;; ocbwb @%0
;; extu.w %0,%2
;; or %1,%2
;; mov.l %0,@%2
;; This description is likely inexact, but this pattern should not actually
;; appear when compiling for sh4-300; we should use isbi instead.
;; If a -mtune option is added later, we should use the icache array
@ -197,7 +193,6 @@
;; since there are no instructions that contend for memory access early.
;; We could, of course, provide exact scheduling information for specific
;; sfuncs, if that should prove useful.
(define_insn_reservation "sh4_300_call" 16
(and (eq_attr "pipe_model" "sh4_300")
(eq_attr "type" "call,sfunc"))
@ -265,7 +260,6 @@
(eq_attr "type" "dfdiv"))
"sh4_300_issue+sh4_300_fpu+sh4_300_fds,sh4_300_fds*31")
;; ??? We don't really want these for sh4-300.
;; this pattern itself is likely to finish in 3 cycles, but also
;; to disrupt branch prediction for taken branches for the following

42
gcc/config/sh/sh4.md
View File

@ -41,35 +41,29 @@
;; Two automata are defined to reduce number of states
;; which a single large automaton will have. (Factoring)
(define_automaton "inst_pipeline,fpu_pipe")
;; This unit is basically the decode unit of the processor.
;; Since SH4 is a dual issue machine,it is as if there are two
;; units so that any insn can be processed by either one
;; of the decoding unit.
(define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
;; The fixed point arithmetic calculator(?? EX Unit).
(define_cpu_unit "int" "inst_pipeline")
;; f1_1 and f1_2 are floating point units.Actually there is
;; a f1 unit which can overlap with other f1 unit but
;; not another F1 unit.It is as though there were two
;; f1 units.
(define_cpu_unit "f1_1,f1_2" "fpu_pipe")
;; The floating point units (except FS - F2 always precedes it.)
(define_cpu_unit "F0,F1,F2,F3" "fpu_pipe")
;; This is basically the MA unit of SH4
;; used in LOAD/STORE pipeline.
(define_cpu_unit "memory" "inst_pipeline")
;; However, there are LS group insns that don't use it, even ones that
@ -85,12 +79,10 @@
;; ----------------------------------------------------
;; This reservation is to simplify the dual issue description.
(define_reservation "issue" "pipe_01|pipe_02")
;; This is to express the locking of D stage.
;; Note that the issue of a CO group insn also effectively locks the D stage.
(define_reservation "d_lock" "pipe_01+pipe_02")
;; Every FE instruction but fipr / ftrv starts with issue and this.
@ -98,12 +90,10 @@
;; This is to simplify description where F1,F2,FS
;; are used simultaneously.
(define_reservation "fpu" "F1+F2")
;; This is to highlight the fact that f1
;; cannot overlap with F1.
(exclusion_set "f1_1,f1_2" "F1")
(define_insn_reservation "nil" 0 (eq_attr "type" "nil") "nothing")
@ -113,14 +103,12 @@
;; for one cycle.
;; Group: MT
(define_insn_reservation "reg_mov" 0
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "move"))
"issue")
;; Group: LS
(define_insn_reservation "freg_mov" 0
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fmove"))
@ -145,7 +133,6 @@
;; Group: MT
;; Latency: 1
;; Issue Rate: 1
(define_insn_reservation "mt" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mt_group"))
@ -155,7 +142,6 @@
;; Group: EX
;; Latency: 1
;; Issue Rate: 1
(define_insn_reservation "sh4_simple_arith" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "insn_class" "ex_group"))
@ -178,7 +164,6 @@
;; Group: LS
;; Latency: 2
;; Issue Rate: 1
(define_insn_reservation "sh4_load" 2
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "load,pcload"))
@ -220,7 +205,6 @@
;; Group: LS
;; Latency: 1
;; Issue Rate: 1
(define_insn_reservation "sh4_gp_fpul" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "gp_fpul"))
@ -230,7 +214,6 @@
;; Group: LS
;; Latency: 3
;; Issue Rate: 1
(define_insn_reservation "sh4_fpul_gp" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fpul_gp"))
@ -246,7 +229,6 @@
;; ??? If the branch is likely, we might want to fill the delay slot;
;; if the branch is likely, but not very likely, should we pretend to use
;; a resource that CO instructions use, to get a pairable delay slot insn?
(define_insn_reservation "sh4_branch" 1
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "cbranch,jump"))
@ -258,7 +240,6 @@
;; Issue Rate: 2
;; ??? Scheduling happens before branch shortening, and hence jmp and braf
;; can't be distinguished from bra for the "jump" pattern.
(define_insn_reservation "sh4_return" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "return,jump_ind"))
@ -270,7 +251,6 @@
;; Issue Rate: 5
;; this instruction can be executed in any of the pipelines
;; and blocks the pipeline for next 4 stages.
(define_insn_reservation "sh4_return_from_exp" 5
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "rte"))
@ -280,8 +260,11 @@
;; Group: CO
;; Latency: 1-5
;; Issue Rate: 1
;; cwb is used for the sequence ocbwb @%0; extu.w %0,%2; or %1,%2; mov.l %0,@%2
;; cwb is used for the sequence
;; ocbwb @%0
;; extu.w %0,%2
;; or %1,%2
;; mov.l %0,@%2
;; ocbwb on its own would be "d_lock,nothing,memory*5"
(define_insn_reservation "ocbwb" 6
(and (eq_attr "pipe_model" "sh4")
@ -298,7 +281,6 @@
;; or when we are doing a function call - and we don't do inter-function
;; scheduling. For the function call case, it's really best that we end with
;; something that models an rts.
(define_insn_reservation "sh4_lds_to_pr" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "prset") )
@ -311,7 +293,6 @@
;; since there are no instructions that contend for memory access early.
;; We could, of course, provide exact scheduling information for specific
;; sfuncs, if that should prove useful.
(define_insn_reservation "sh4_call" 16
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "call,sfunc"))
@ -322,7 +303,6 @@
;; Latency: 3
;; Issue Rate: 2
;; The SX unit is blocked for last 2 cycles.
(define_insn_reservation "ldsmem_to_pr" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "pload"))
@ -333,7 +313,6 @@
;; Latency: 2
;; Issue Rate: 2
;; The SX unit in second and third cycles.
(define_insn_reservation "sts_from_pr" 2
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "prget"))
@ -343,7 +322,6 @@
;; Group: CO
;; Latency: 2
;; Issue Rate: 2
(define_insn_reservation "sh4_prstore_mem" 2
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "pstore"))
@ -354,7 +332,6 @@
;; Latency: 4
;; Issue Rate: 1
;; F1 is blocked for last three cycles.
(define_insn_reservation "fpscr_load" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "gp_fpscr"))
@ -366,7 +343,6 @@
;; Latency to update Rn is 1 and latency to update FPSCR is 4
;; Issue Rate: 1
;; F1 is blocked for last three cycles.
(define_insn_reservation "fpscr_load_mem" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mem_fpscr"))
@ -377,7 +353,6 @@
;; Group: CO
;; Latency: 4 / 4
;; Issue Rate: 2
(define_insn_reservation "multi" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "smpy,dmpy"))
@ -387,7 +362,6 @@
;; Group: CO
;; Latency: 3
;; Issue Rate: 1
(define_insn_reservation "sh4_mac_gp" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "mac_gp,gp_mac,mem_mac"))
@ -399,7 +373,6 @@
;; Group: FE
;; Latency: 3/4
;; Issue Rate: 1
(define_insn_reservation "fp_arith" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fp,fp_cmp"))
@ -424,7 +397,6 @@
;; Latency: 12/13 (FDIV); 11/12 (FSQRT)
;; Issue Rate: 1
;; We describe fdiv here; fsqrt is actually one cycle faster.
(define_insn_reservation "fp_div" 12
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "fdiv"))
@ -435,7 +407,6 @@
;; Group: FE
;; Latency: (3,4)/5
;; Issue Rate: 1
(define_insn_reservation "dp_float" 4
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_conv"))
@ -445,7 +416,6 @@
;; Group: FE
;; Latency: (7,8)/9
;; Issue Rate: 1
(define_insn_reservation "fp_double_arith" 8
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_arith,dfp_mul"))
@ -455,7 +425,6 @@
;; Group: CO
;; Latency: 3/5
;; Issue Rate: 2
(define_insn_reservation "fp_double_cmp" 3
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfp_cmp"))
@ -465,7 +434,6 @@
;; Group: FE
;; Latency: (24,25)/26
;; Issue Rate: 1
(define_insn_reservation "dp_div" 25
(and (eq_attr "pipe_model" "sh4")
(eq_attr "type" "dfdiv"))

2
gcc/config/sh/sh4a.md
View File

@ -19,7 +19,6 @@
;; The following description models the SH4A pipeline
;; using the DFA based scheduler.
(define_automaton "sh4a")
(define_cpu_unit "sh4a_ex" "sh4a")
@ -35,7 +34,6 @@
(define_reservation "ID_or" "sh4a_ex|sh4a_ls")
(define_reservation "ID_and" "sh4a_ex+sh4a_ls")
;; =======================================================
;; Locking Descriptions

4
gcc/config/sh/superh.h
View File

@ -29,7 +29,6 @@ along with GCC; see the file COPYING3. If not see
This file is intended to override sh.h. */
#ifndef _SUPERH_H
#define _SUPERH_H
#endif
@ -55,7 +54,8 @@ along with GCC; see the file COPYING3. If not see
#endif
/* This is used by the link spec if the boardspecs file is not used (for whatever reason).
/* This is used by the link spec if the boardspecs file is not used
(for whatever reason).
If the boardspecs file overrides this then an alternative can be used. */
#undef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS \

12
gcc/config/sh/ushmedia.h
View File

@ -1010,7 +1010,8 @@ sh_media_FMTRXSUB_S (const void *mtrxg, const void *mtrxh, void *mtrxf)
__inline__ static
void
sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, void *fvf)
sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi,
void *fvf)
{
sh_media_FTRV_S (mtrxg, fvh, fvf);
sh_media_FVADD_S (fvf, fvi, fvf);
@ -1018,7 +1019,8 @@ sh_media_FTRVADD_S (const void *mtrxg, const void *fvh, const void *fvi, void *f
__inline__ static
void
sh_media_FTRVSUB_S (const void *mtrxg, const void *fvh, const void *fvi, void *fvf)
sh_media_FTRVSUB_S (const void *mtrxg, const void *fvh, const void *fvi,
void *fvf)
{
sh_media_FTRV_S (mtrxg, fvh, fvf);
sh_media_FVSUB_S (fvf, fvi, fvf);
@ -1045,7 +1047,8 @@ sh_media_FMTRXMUL_S (const void *mtrxg, const void *mtrxh, void *mtrxf)
__inline__ static
void
sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, const void *mtrxi, void *mtrxf)
sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh,
const void *mtrxi, void *mtrxf)
{
const __GCC_FV *g = mtrxg, *i = mtrxi;
__GCC_FV *f = mtrxf;
@ -1064,7 +1067,8 @@ sh_media_FMTRXMULADD_S (const void *mtrxg, const void *mtrxh, const void *mtrxi,
__inline__ static
void
sh_media_FMTRXMULSUB_S (const void *mtrxg, const void *mtrxh, const void *mtrxi, void *mtrxf)
sh_media_FMTRXMULSUB_S (const void *mtrxg, const void *mtrxh,
const void *mtrxi, void *mtrxf)
{
const __GCC_FV *g = mtrxg, *i = mtrxi;
__GCC_FV *f = mtrxf;