sh.md (divsi3_i4_media): Use match_operand for input values rather than hard registers.
* sh.md (divsi3_i4_media): Use match_operand for input values rather than hard registers. (divsi3 - TARGET_SHMEDIA_FPU case): Don't ferry values unnecessarily through hard registers. Keep copies of pseudo registers outside of the libcall sequence. * sh.md (casesi_shift_media): Add modes. From-SVN: r52732
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@ -1,4 +1,12 @@
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Wed Apr 24 21:20:58 2002 J"orn Rennecke <joern.rennecke@superh.com>
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Wed Apr 24 21:25:59 2002 J"orn Rennecke <joern.rennecke@superh.com>
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* sh.md (divsi3_i4_media): Use match_operand for input values
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rather than hard registers.
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(divsi3 - TARGET_SHMEDIA_FPU case): Don't ferry values
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unnecessarily through hard registers. Keep copies of pseudo
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registers outside of the libcall sequence.
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* sh.md (casesi_shift_media): Add modes.
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* sh.h (RETURN_IN_MEMORY): Return variable size BLKmode
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values in memory.
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@ -1412,21 +1412,17 @@
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"blink %1, r18")
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(define_expand "divsi3_i4_media"
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[(set (match_dup 2) (reg:SI R4_REG))
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(set (match_dup 3) (reg:SI R5_REG))
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(set (match_dup 4) (float:DF (match_dup 2)))
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(set (match_dup 5) (float:DF (match_dup 3)))
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(set (match_dup 6) (div:DF (match_dup 4) (match_dup 5)))
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[(set (match_dup 3) (float:DF (match_operand:SI 1 "register_operand" "r")))
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(set (match_dup 4) (float:DF (match_operand:SI 2 "register_operand" "r")))
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(set (match_dup 5) (div:DF (match_dup 3) (match_dup 4)))
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(set (match_operand:SI 0 "register_operand" "=r")
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(fix:SI (match_dup 6)))]
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(fix:SI (match_dup 5)))]
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"TARGET_SHMEDIA_FPU"
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"
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{
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operands[2] = gen_reg_rtx (SImode);
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operands[3] = gen_reg_rtx (SImode);
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operands[3] = gen_reg_rtx (DFmode);
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operands[4] = gen_reg_rtx (DFmode);
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operands[5] = gen_reg_rtx (DFmode);
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operands[6] = gen_reg_rtx (DFmode);
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}")
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(define_insn "divsi3_i4"
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@ -1472,7 +1468,7 @@
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""
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"
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{
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rtx first, last;
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rtx first = 0, last;
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operands[3] = gen_reg_rtx (Pmode);
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/* Emit the move of the address to a pseudo outside of the libcall. */
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@ -1486,7 +1482,12 @@
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last = gen_divsi3_i4 (operands[0], operands[3]);
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}
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else if (TARGET_SHMEDIA_FPU)
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last = gen_divsi3_i4_media (operands[0]);
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{
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operands[1] = force_reg (SImode, operands[1]);
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operands[2] = force_reg (SImode, operands[2]);
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last = gen_divsi3_i4_media (operands[0], operands[1], operands[2]);
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first = XVECEXP (last, 0, 0);
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}
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else if (TARGET_SH5)
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{
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emit_move_insn (operands[3],
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@ -1511,8 +1512,11 @@
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emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
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last = gen_divsi3_i1 (operands[0], operands[3]);
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}
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first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
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emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
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if (! first)
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{
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first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
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emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
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}
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last = emit_insn (last);
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/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
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invariant code motion can move it. */
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@ -6458,9 +6462,10 @@
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[(set_attr "length" "4")])
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(define_insn "casesi_shift_media"
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[(set (match_operand 0 "arith_reg_operand" "=r")
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(ashift (match_operand 1 "arith_reg_operand" "r")
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(unspec [(label_ref:DI (match_operand 2 "" ""))] 2)))]
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[(set (match_operand:DI 0 "arith_reg_operand" "=r")
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(ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
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(unspec:DI [(label_ref:DI (match_operand 2 "" ""))]
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UNSPEC_CASESI)))]
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"TARGET_SHMEDIA"
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"*
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{
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