RISC-V: Implement misc macro for vector extensions.
See also: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21 gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_flag_table): Update flag name and mask name. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define misc macro for vector extensions. * config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): Rename to ... (MASK_VECTOR_ELEN_32): ... this. (MASK_VECTOR_EEW_64): Rename to ... (MASK_VECTOR_ELEN_64): ... this. (MASK_VECTOR_EEW_FP_32): Rename to ... (MASK_VECTOR_ELEN_FP_32): ... this. (MASK_VECTOR_EEW_FP_64): Rename to ... (MASK_VECTOR_ELEN_FP_64): ... this. (TARGET_VECTOR_ELEN_32): New. (TARGET_VECTOR_ELEN_64): Ditto. (TARGET_VECTOR_ELEN_FP_32): Ditto. (TARGET_VECTOR_ELEN_FP_64): Ditto. (TARGET_MIN_VLEN): Ditto. * config/riscv/riscv.opt (riscv_vector_eew_flags): Rename to ... (riscv_vector_elen_flags): ... this. gcc/testsuite/ChangeLog: * gcc.target/riscv/arch-13.c: New. * gcc.target/riscv/arch-14.c: Ditto. * gcc.target/riscv/arch-15.c: Ditto. * gcc.target/riscv/predef-18.c: Ditto. * gcc.target/riscv/predef-19.c: Ditto. * gcc.target/riscv/predef-20.c: Ditto.
This commit is contained in:
Kito Cheng
parent
e767da23de
commit
5177634148
@ -1116,16 +1116,16 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
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{"zve64f", &gcc_options::x_target_flags, MASK_VECTOR},
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{"zve64d", &gcc_options::x_target_flags, MASK_VECTOR},
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/* We don't need to put complete EEW/EEW_FP info here, due to the
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/* We don't need to put complete ELEN/ELEN_FP info here, due to the
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implication relation of vector extension.
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e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_EEW_FP_64,
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MASK_VECTOR_EEW_FP_32, MASK_VECTOR_EEW_64 and MASK_VECTOR_EEW_32
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e.g. v -> zve64d ... zve32x, so v has set MASK_VECTOR_ELEN_FP_64,
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MASK_VECTOR_ELEN_FP_32, MASK_VECTOR_ELEN_64 and MASK_VECTOR_ELEN_32
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due to the extension implication. */
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{"zve32x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_32},
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{"zve32f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
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{"zve64x", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_64},
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{"zve64f", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_32},
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{"zve64d", &gcc_options::x_riscv_vector_eew_flags, MASK_VECTOR_EEW_FP_64},
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{"zve32x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_32},
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{"zve32f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
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{"zve64x", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
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{"zve64f", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
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{"zve64d", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64},
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{"zvl32b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
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{"zvl64b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
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@ -104,6 +104,24 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
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}
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if (TARGET_MIN_VLEN != 0)
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builtin_define_with_int_value ("__riscv_v_min_vlen", TARGET_MIN_VLEN);
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if (TARGET_VECTOR_ELEN_64)
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builtin_define_with_int_value ("__riscv_v_elen", 64);
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else if (TARGET_VECTOR_ELEN_32)
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builtin_define_with_int_value ("__riscv_v_elen", 32);
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if (TARGET_VECTOR_ELEN_FP_64)
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builtin_define_with_int_value ("__riscv_v_elen_fp", 64);
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else if (TARGET_VECTOR_ELEN_FP_32)
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builtin_define_with_int_value ("__riscv_v_elen_fp", 32);
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else if (TARGET_MIN_VLEN != 0)
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builtin_define_with_int_value ("__riscv_v_elen_fp", 0);
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if (TARGET_MIN_VLEN)
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builtin_define ("__riscv_vector");
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/* Define architecture extension test macros. */
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builtin_define_with_int_value ("__riscv_arch_test", 1);
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@ -105,10 +105,19 @@ enum stack_protector_guard {
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#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
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#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
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#define MASK_VECTOR_EEW_32 (1 << 0)
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#define MASK_VECTOR_EEW_64 (1 << 1)
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#define MASK_VECTOR_EEW_FP_32 (1 << 2)
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#define MASK_VECTOR_EEW_FP_64 (1 << 3)
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#define MASK_VECTOR_ELEN_32 (1 << 0)
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#define MASK_VECTOR_ELEN_64 (1 << 1)
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#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
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#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
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#define TARGET_VECTOR_ELEN_32 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
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#define TARGET_VECTOR_ELEN_64 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
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#define TARGET_VECTOR_ELEN_FP_32 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
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#define TARGET_VECTOR_ELEN_FP_64 \
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((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
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#define MASK_ZVL32B (1 << 0)
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#define MASK_ZVL64B (1 << 1)
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@ -136,4 +145,12 @@ enum stack_protector_guard {
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#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
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#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
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/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
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set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
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popcount to caclulate the minimal VLEN. */
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#define TARGET_MIN_VLEN \
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((riscv_zvl_flags == 0) \
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? 0 \
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: 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
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#endif /* ! GCC_RISCV_OPTS_H */
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@ -204,7 +204,7 @@ TargetVariable
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int riscv_zk_subext
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TargetVariable
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int riscv_vector_eew_flags
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int riscv_vector_elen_flags
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TargetVariable
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int riscv_zvl_flags
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5
gcc/testsuite/gcc.target/riscv/arch-13.c
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5
gcc/testsuite/gcc.target/riscv/arch-13.c
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@ -0,0 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv32gcv -mabi=ilp32 -mcmodel=medlow" } */
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int foo()
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{
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}
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5
gcc/testsuite/gcc.target/riscv/arch-14.c
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5
gcc/testsuite/gcc.target/riscv/arch-14.c
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@ -0,0 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv32gc_zve64f_zvl128b -mabi=ilp32 -mcmodel=medlow" } */
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int foo()
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{
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}
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5
gcc/testsuite/gcc.target/riscv/arch-15.c
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5
gcc/testsuite/gcc.target/riscv/arch-15.c
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@ -0,0 +1,5 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv32gcv_zvl128b -mabi=ilp32 -mcmodel=medlow" } */
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int foo()
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{
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}
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84
gcc/testsuite/gcc.target/riscv/predef-18.c
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84
gcc/testsuite/gcc.target/riscv/predef-18.c
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@ -0,0 +1,84 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv64gcv -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */
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int main () {
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#ifndef __riscv_arch_test
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#error "__riscv_arch_test"
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#endif
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#if __riscv_xlen != 64
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#error "__riscv_xlen"
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#endif
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#if !defined(__riscv_i)
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#error "__riscv_i"
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#endif
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#if !defined(__riscv_c)
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#error "__riscv_c"
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#endif
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#if defined(__riscv_e)
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#error "__riscv_e"
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#endif
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#if !defined(__riscv_a)
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#error "__riscv_a"
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#endif
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#if !defined(__riscv_m)
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#error "__riscv_m"
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#endif
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#if !defined(__riscv_f)
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#error "__riscv_f"
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#endif
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#if !defined(__riscv_d)
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#error "__riscv_d"
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#endif
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#if !defined(__riscv_v)
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#error "__riscv_v"
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#endif
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#if !defined(__riscv_zvl128b)
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#error "__riscv_zvl128b"
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#endif
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#if !defined(__riscv_zvl64b)
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#error "__riscv_zvl64b"
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#endif
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#if !defined(__riscv_zvl32b)
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#error "__riscv_zvl32b"
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#endif
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#if !defined(__riscv_vector)
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#error "__riscv_vector"
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#endif
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#if !defined(__riscv_v_min_vlen)
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#error "__riscv_v_min_vlen"
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#if __riscv_v_min_vlen != 128
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#error "__riscv_v_elen != 128"
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#endif
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#endif
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#if !defined(__riscv_v_elen)
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#error "__riscv_v_elen"
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#if __riscv_v_elen != 64
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#error "__riscv_v_elen != 64"
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#endif
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#endif
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#if !defined(__riscv_v_elen_fp)
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#error "__riscv_v_elen_fp"
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#if __riscv_v_elen_fp != 64
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#error "__riscv_v_elen_fp != 64"
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#endif
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#endif
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return 0;
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}
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88
gcc/testsuite/gcc.target/riscv/predef-19.c
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88
gcc/testsuite/gcc.target/riscv/predef-19.c
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@ -0,0 +1,88 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */
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int main () {
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#ifndef __riscv_arch_test
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#error "__riscv_arch_test"
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#endif
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#if __riscv_xlen != 64
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#error "__riscv_xlen"
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#endif
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#if !defined(__riscv_i)
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#error "__riscv_i"
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#endif
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#if !defined(__riscv_c)
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#error "__riscv_c"
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#endif
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#if defined(__riscv_e)
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#error "__riscv_e"
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#endif
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#if !defined(__riscv_a)
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#error "__riscv_a"
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#endif
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#if !defined(__riscv_m)
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#error "__riscv_m"
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#endif
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#if !defined(__riscv_f)
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#error "__riscv_f"
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#endif
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#if !defined(__riscv_d)
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#error "__riscv_d"
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#endif
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#if defined(__riscv_v)
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#error "__riscv_v"
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#endif
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#if defined(__riscv_zvl128b)
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#error "__riscv_zvl128b"
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#endif
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#if defined(__riscv_zvl64b)
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#error "__riscv_zvl64b"
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#endif
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#if !defined(__riscv_zvl32b)
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#error "__riscv_zvl32b"
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#endif
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#if !defined(__riscv_zve32x)
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#error "__riscv_zve32x"
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#endif
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#if !defined(__riscv_vector)
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#error "__riscv_vector"
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#endif
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#if !defined(__riscv_v_min_vlen)
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#error "__riscv_v_min_vlen"
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#if __riscv_v_min_vlen != 32
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#error "__riscv_v_elen != 32"
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#endif
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#endif
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#if !defined(__riscv_v_elen)
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#error "__riscv_v_elen"
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#if __riscv_v_elen != 32
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#error "__riscv_v_elen != 32"
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#endif
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#endif
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#if !defined(__riscv_v_elen_fp)
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#error "__riscv_v_elen_fp"
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#if __riscv_v_elen_fp != 0
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#error "__riscv_v_elen_fp != 0"
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#endif
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#endif
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return 0;
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}
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84
gcc/testsuite/gcc.target/riscv/predef-20.c
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84
gcc/testsuite/gcc.target/riscv/predef-20.c
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@ -0,0 +1,84 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */
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int main () {
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#ifndef __riscv_arch_test
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#error "__riscv_arch_test"
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#endif
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#if __riscv_xlen != 64
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#error "__riscv_xlen"
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#endif
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#if !defined(__riscv_i)
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#error "__riscv_i"
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#endif
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#if !defined(__riscv_c)
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#error "__riscv_c"
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#endif
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#if defined(__riscv_e)
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#error "__riscv_e"
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#endif
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#if !defined(__riscv_a)
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#error "__riscv_a"
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#endif
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#if !defined(__riscv_m)
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#error "__riscv_m"
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#endif
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#if !defined(__riscv_f)
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#error "__riscv_f"
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#endif
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#if !defined(__riscv_d)
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#error "__riscv_d"
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#endif
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#if !defined(__riscv_v)
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#error "__riscv_v"
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#endif
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#if !defined(__riscv_zvl128b)
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#error "__riscv_zvl128b"
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#endif
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#if !defined(__riscv_zvl64b)
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#error "__riscv_zvl64b"
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#endif
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#if !defined(__riscv_zvl32b)
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#error "__riscv_zvl32b"
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#endif
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#if !defined(__riscv_vector)
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#error "__riscv_vector"
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#endif
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#if !defined(__riscv_v_min_vlen)
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#error "__riscv_v_min_vlen"
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#if __riscv_v_min_vlen != 512
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#error "__riscv_v_elen != 512"
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#endif
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#endif
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#if !defined(__riscv_v_elen)
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#error "__riscv_v_elen"
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#if __riscv_v_elen != 64
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#error "__riscv_v_elen != 64"
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#endif
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#endif
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#if !defined(__riscv_v_elen_fp)
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#error "__riscv_v_elen_fp"
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#if __riscv_v_elen_fp != 64
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#error "__riscv_v_elen_fp != 64"
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#endif
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#endif
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return 0;
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}
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