2097.md (z10_fhex): Remove insn reservation.
2010-06-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/s390/2097.md (z10_fhex): Remove insn reservation. * config/s390/s390.md (UNSPEC_COPYSIGN): Remove unused constant. (*mov<mode>_64 TD_TF, *mov<mode>_31 TD_TF, *mov<mode>_64dfp DD_DF, *mov<mode>_64 DD_DF, *mov<mode>_31, mov<mode>): Remove load zero instruction. * config/s390/s390.c: Don't accept fp zeros as valid constants anymore. From-SVN: r160149
This commit is contained in:
parent
59ed407a06
commit
51eab27d21
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@ -1,3 +1,13 @@
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2010-06-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* config/s390/2097.md (z10_fhex): Remove insn reservation.
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* config/s390/s390.md (UNSPEC_COPYSIGN): Remove unused constant.
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(*mov<mode>_64 TD_TF, *mov<mode>_31 TD_TF, *mov<mode>_64dfp DD_DF,
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*mov<mode>_64 DD_DF, *mov<mode>_31, mov<mode>): Remove load zero
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instruction.
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* config/s390/s390.c: Don't accept fp zeros as valid constants
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anymore.
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2010-05-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
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* config/s390/s390.md (movqi): Fix typo ('*' -> '#').
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@ -466,15 +466,6 @@
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(eq_attr "type" "fsimpdf,fmuldf"))
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"z10_e1_BOTH, z10_Gate_FP")
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; LOAD ZERO produces a hex value but we need bin. Using the stage 7
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; bypass causes an exception for format conversion which is very
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; expensive. So, make sure subsequent instructions only get the zero
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; in the normal way.
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(define_insn_reservation "z10_fhex" 12
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(and (eq_attr "cpu" "z10")
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(eq_attr "type" "fhex"))
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"z10_e1_BOTH, z10_Gate_FP")
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(define_insn_reservation "z10_fsimpsf" 6
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(and (eq_attr "cpu" "z10")
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(eq_attr "type" "fsimpsf,fmulsf"))
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@ -2794,11 +2794,6 @@ legitimate_reload_constant_p (rtx op)
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&& larl_operand (op, VOIDmode))
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return true;
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/* Accept lzXX operands. */
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if (GET_CODE (op) == CONST_DOUBLE
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&& CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, 'G', "G"))
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return true;
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/* Accept double-word operands that can be split. */
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if (GET_CODE (op) == CONST_INT
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&& trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
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@ -105,11 +105,8 @@
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(UNSPEC_SP_SET 700)
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(UNSPEC_SP_TEST 701)
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; Copy sign instructions
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(UNSPEC_COPYSIGN 800)
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; Test Data Class (TDC)
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(UNSPEC_TDC_INSN 900)
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(UNSPEC_TDC_INSN 800)
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])
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;;
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@ -1956,11 +1953,10 @@
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"")
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(define_insn "*mov<mode>_64"
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[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o")
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(match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))]
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[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o, d,QS, d,o")
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(match_operand:TD_TF 1 "general_operand" " f,o,f,QS, d,dRT,d"))]
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"TARGET_64BIT"
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"@
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lzxr\t%0
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lxr\t%0,%1
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#
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#
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@ -1968,20 +1964,19 @@
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stmg\t%1,%N1,%S0
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#
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#"
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[(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*")
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(set_attr "type" "fhex,fsimptf,*,*,lm,stm,*,*")])
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[(set_attr "op_type" "RRE,*,*,RSY,RSY,*,*")
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(set_attr "type" "fsimptf,*,*,lm,stm,*,*")])
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(define_insn "*mov<mode>_31"
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[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o")
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(match_operand:TD_TF 1 "general_operand" " G,f,o,f"))]
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[(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,o")
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(match_operand:TD_TF 1 "general_operand" " f,o,f"))]
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"!TARGET_64BIT"
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"@
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lzxr\t%0
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lxr\t%0,%1
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#
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#"
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[(set_attr "op_type" "RRE,RRE,*,*")
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(set_attr "type" "fhex,fsimptf,*,*")])
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[(set_attr "op_type" "RRE,*,*")
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(set_attr "type" "fsimptf,*,*")])
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; TFmode in GPRs splitters
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@ -2072,12 +2067,11 @@
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(define_insn "*mov<mode>_64dfp"
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[(set (match_operand:DD_DF 0 "nonimmediate_operand"
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"=f,f,f,d,f,f,R,T,d, d,RT")
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"=f,f,d,f,f,R,T,d, d,RT")
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(match_operand:DD_DF 1 "general_operand"
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" G,f,d,f,R,T,f,f,d,RT, d"))]
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" f,d,f,R,T,f,f,d,RT, d"))]
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"TARGET_64BIT && TARGET_DFP"
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"@
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lzdr\t%0
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ldr\t%0,%1
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ldgr\t%0,%1
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lgdr\t%0,%1
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@ -2088,28 +2082,17 @@
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lgr\t%0,%1
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lg\t%0,%1
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stg\t%1,%0"
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[(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
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(set_attr "type" "fhex,floaddf,floaddf,floaddf,floaddf,floaddf,
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[(set_attr "op_type" "RR,RRE,RRE,RX,RXY,RX,RXY,RRE,RXY,RXY")
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(set_attr "type" "floaddf,floaddf,floaddf,floaddf,floaddf,
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fstoredf,fstoredf,lr,load,store")
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(set_attr "z10prop" "*,
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*,
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*,
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*,
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*,
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*,
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*,
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*,
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z10_fr_E1,
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z10_fwd_A3,
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z10_rec")
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(set_attr "z10prop" "*,*,*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")
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])
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(define_insn "*mov<mode>_64"
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[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d, d,RT")
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(match_operand:DD_DF 1 "general_operand" "G,f,R,T,f,f,d,RT, d"))]
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[(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,R,T,d, d,RT")
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(match_operand:DD_DF 1 "general_operand" "f,R,T,f,f,d,RT, d"))]
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"TARGET_64BIT"
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"@
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lzdr\t%0
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ldr\t%0,%1
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ld\t%0,%1
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ldy\t%0,%1
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@ -2118,27 +2101,18 @@
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lgr\t%0,%1
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lg\t%0,%1
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stg\t%1,%0"
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[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
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(set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY")
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(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
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fstore<mode>,fstore<mode>,lr,load,store")
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(set_attr "z10prop" "*,
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*,
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*,
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*,
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*,
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*,
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z10_fr_E1,
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z10_fwd_A3,
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z10_rec")])
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(set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_rec")])
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(define_insn "*mov<mode>_31"
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[(set (match_operand:DD_DF 0 "nonimmediate_operand"
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"=f,f,f,f,R,T,d,d,Q,S, d,o")
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"=f,f,f,R,T,d,d,Q,S, d,o")
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(match_operand:DD_DF 1 "general_operand"
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" G,f,R,T,f,f,Q,S,d,d,dPRT,d"))]
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" f,R,T,f,f,Q,S,d,d,dPRT,d"))]
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"!TARGET_64BIT"
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"@
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lzdr\t%0
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ldr\t%0,%1
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ld\t%0,%1
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ldy\t%0,%1
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@ -2150,8 +2124,8 @@
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stmy\t%1,%N1,%S0
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#
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#"
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[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
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(set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*")
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(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
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fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*")])
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(define_split
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@ -2201,12 +2175,11 @@
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(define_insn "mov<mode>"
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[(set (match_operand:SD_SF 0 "nonimmediate_operand"
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"=f,f,f,f,R,T,d,d,d,R,T")
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"=f,f,f,R,T,d,d,d,R,T")
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(match_operand:SD_SF 1 "general_operand"
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" G,f,R,T,f,f,d,R,T,d,d"))]
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" f,R,T,f,f,d,R,T,d,d"))]
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""
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"@
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lzer\t%0
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ler\t%0,%1
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le\t%0,%1
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ley\t%0,%1
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@ -2217,20 +2190,10 @@
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ly\t%0,%1
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st\t%1,%0
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sty\t%1,%0"
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[(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
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(set_attr "type" "fhex,fload<mode>,fload<mode>,fload<mode>,
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[(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY")
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(set_attr "type" "fload<mode>,fload<mode>,fload<mode>,
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fstore<mode>,fstore<mode>,lr,load,load,store,store")
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(set_attr "z10prop" "*,
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*,
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*,
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*,
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*,
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*,
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z10_fr_E1,
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z10_fwd_A3,
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z10_fwd_A3,
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z10_rec,
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z10_rec")])
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(set_attr "z10prop" "*,*,*,*,*,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec")])
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;
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; movcc instruction pattern
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