OpenE2K/gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[AArch64, ILP32] 3/6 Change tests to be ILP32-friendly.

Browse Source 
gcc/testsuite/

	* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
	* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
	type from long to long long.
	* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
	to have effective-target keywords of lp64 and ilp32.
	* gcc.target/aarch64/fcvt_double_int.c: Likewise.
	* gcc.target/aarch64/fcvt_double_long.c: Likewise.
	* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
	* gcc.target/aarch64/fcvt_float_int.c: Likewise.
	* gcc.target/aarch64/fcvt_float_long.c: Likewise.
	* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
	* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.

From-SVN: r201166
This commit is contained in:
Yufeng Zhang 2013-07-23 12:23:05 +00:00 committed by Yufeng Zhang
parent 28514ddab4
commit 527b11f91d
13 changed files with 89 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,20 @@
2013-07-23 Yufeng Zhang <yufeng.zhang@arm.com>
* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
type from long to long long.
* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
to have effective-target keywords of lp64 and ilp32.
* gcc.target/aarch64/fcvt_double_int.c: Likewise.
* gcc.target/aarch64/fcvt_double_long.c: Likewise.
* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
* gcc.target/aarch64/fcvt_float_int.c: Likewise.
* gcc.target/aarch64/fcvt_float_long.c: Likewise.
* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.
2013-07-23 Tom Tromey <tromey@redhat.com>
Joseph Myers <joseph@codesourcery.com>

1
gcc/testsuite/gcc.dg/20020219-1.c
View File

@ -13,6 +13,7 @@
/* { dg-do run } */
/* { dg-options "-O2" } */
/* { dg-options "-O2 -mdisable-indexing" { target hppa*-*-hpux* } } */
/* { dg-skip-if "" { aarch64*-*-* && ilp32 } { "*" } { "" } } */
/* { dg-skip-if "" { "ia64-*-hpux*" } "*" "-mlp64" } */
/* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */

8
gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
View File

@ -9,10 +9,10 @@
struct y
{
long p;
long q;
long r;
long s;
long long p;
long long q;
long long r;
long long s;
} v = { 1, 2, 3, 4 };
struct z

6
gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
View File

@ -39,5 +39,7 @@ atomic_fetch_or_RELAXED (long a)
return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
}
/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */

10
gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
View File

@ -8,8 +8,10 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 } } */

12
gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
View File

@ -7,7 +7,11 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 } } */
/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */

6
gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
View File

@ -8,8 +8,10 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 } } */

18
gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
View File

@ -7,9 +7,15 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */

10
gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
View File

@ -8,8 +8,10 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */

12
gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
View File

@ -7,7 +7,11 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 } } */
/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */

6
gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
View File

@ -8,8 +8,10 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */

18
gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
View File

@ -7,9 +7,15 @@
#include "fcvt.x"
/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 } } */
/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */

6
gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
View File

@ -4,11 +4,11 @@
typedef signed char S8_t;
typedef signed short S16_t;
typedef signed int S32_t;
typedef signed long S64_t;
typedef signed long long S64_t;
typedef signed char *__restrict__ pS8_t;
typedef signed short *__restrict__ pS16_t;
typedef signed int *__restrict__ pS32_t;
typedef signed long *__restrict__ pS64_t;
typedef signed long long *__restrict__ pS64_t;
typedef unsigned char U8_t;
typedef unsigned short U16_t;
typedef unsigned int U32_t;
@ -16,7 +16,7 @@ typedef unsigned long U64_t;
typedef unsigned char *__restrict__ pU8_t;
typedef unsigned short *__restrict__ pU16_t;
typedef unsigned int *__restrict__ pU32_t;
typedef unsigned long *__restrict__ pU64_t;
typedef unsigned long long *__restrict__ pU64_t;
extern void abort ();