arm-protos.h (arm_sched_autopref): Delete.
* arm-protos.h (arm_sched_autopref): Delete. (tune_params): Re-organize, use enums for flag values. (FUSE_OPS): New macro. * arm.c (ARM_PREFETCH_NOT_BENEFICIAL): Update. (ARM_PREFETCH_BENEFICIAL): Likewise. (ARM_FUSE_NOTHING, ARM_FUSE_MOVW_MOVT): Delete. (arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune) (arm_xscale_tune, arm_9e_tune, arm_marvell_pj4_tune) (arm_v6t2_tune, arm_cortex_tune, arm_cortex_a8_tune) (arm_cortex_a7_tune, arm_cortex_a15_tune, arm_cortex_a53_tune) (arm_cortex_a57_tune, arm_xgene1_tune, arm_cortex_a5_tune) (arm_cortex_a9_tune, arm_cortex_a12_tune, arm_v7m_tune) (arm_cortex_m7_tune, arm_v6m_tune, arm_fa726te_tune): Use new format. (arm_option_override, thumb2_reorg, arm_print_tune_info) (aarch_macro_fusion_pair_p): Update uses of current_tune. * arm.h (LOGCIAL_OP_NON_SHORT_CIRCUIT): Likewise. From-SVN: r223090
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
cc1e0483ae
commit
52c266bab2
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@ -1,3 +1,23 @@
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2015-05-12 Richard Earnshaw <rearnsha@arm.com>
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* arm-protos.h (arm_sched_autopref): Delete.
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(tune_params): Re-organize, use enums for flag values.
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(FUSE_OPS): New macro.
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* arm.c (ARM_PREFETCH_NOT_BENEFICIAL): Update.
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(ARM_PREFETCH_BENEFICIAL): Likewise.
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(ARM_FUSE_NOTHING, ARM_FUSE_MOVW_MOVT): Delete.
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(arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune)
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(arm_xscale_tune, arm_9e_tune, arm_marvell_pj4_tune)
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(arm_v6t2_tune, arm_cortex_tune, arm_cortex_a8_tune)
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(arm_cortex_a7_tune, arm_cortex_a15_tune, arm_cortex_a53_tune)
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(arm_cortex_a57_tune, arm_xgene1_tune, arm_cortex_a5_tune)
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(arm_cortex_a9_tune, arm_cortex_a12_tune, arm_v7m_tune)
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(arm_cortex_m7_tune, arm_v6m_tune, arm_fa726te_tune): Use new
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format.
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(arm_option_override, thumb2_reorg, arm_print_tune_info)
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(aarch_macro_fusion_pair_p): Update uses of current_tune.
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* arm.h (LOGCIAL_OP_NON_SHORT_CIRCUIT): Likewise.
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2015-05-12 Sandra Loosemore <sandra@codesourcery.com>
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* config/nios2/nios2.md (trap, ctrapsi4): Use "trap" instead of
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@ -251,13 +251,6 @@ struct cpu_vec_costs {
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struct cpu_cost_table;
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enum arm_sched_autopref
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{
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ARM_SCHED_AUTOPREF_OFF,
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ARM_SCHED_AUTOPREF_RANK,
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ARM_SCHED_AUTOPREF_FULL
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};
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/* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this
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structure is modified. */
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@ -266,41 +259,57 @@ struct tune_params
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bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
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const struct cpu_cost_table *insn_extra_cost;
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bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
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int (*branch_cost) (bool, bool);
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/* Vectorizer costs. */
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const struct cpu_vec_costs* vec_costs;
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int constant_limit;
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/* Maximum number of instructions to conditionalise. */
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int max_insns_skipped;
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int num_prefetch_slots;
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int l1_cache_size;
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int l1_cache_line_size;
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bool prefer_constant_pool;
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int (*branch_cost) (bool, bool);
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/* Maximum number of instructions to inline calls to memset. */
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int max_insns_inline_memset;
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/* Issue rate of the processor. */
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unsigned int issue_rate;
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/* Explicit prefetch data. */
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struct
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{
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int num_slots;
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int l1_cache_size;
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int l1_cache_line_size;
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} prefetch;
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enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE}
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prefer_constant_pool: 1;
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/* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
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bool prefer_ldrd_strd;
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enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
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/* The preference for non short cirtcuit operation when optimizing for
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performance. The first element covers Thumb state and the second one
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is for ARM state. */
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bool logical_op_non_short_circuit[2];
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/* Vectorizer costs. */
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const struct cpu_vec_costs* vec_costs;
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/* Prefer Neon for 64-bit bitops. */
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bool prefer_neon_for_64bits;
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enum log_op_non_sc {LOG_OP_NON_SC_FALSE, LOG_OP_NON_SC_TRUE};
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log_op_non_sc logical_op_non_short_circuit_thumb: 1;
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log_op_non_sc logical_op_non_short_circuit_arm: 1;
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/* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
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bool disparage_flag_setting_t16_encodings;
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/* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags
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would be set. */
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bool disparage_partial_flag_setting_t16_encodings;
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enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL}
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disparage_flag_setting_t16_encodings: 2;
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enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1;
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/* Prefer to inline string operations like memset by using Neon. */
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bool string_ops_prefer_neon;
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/* Maximum number of instructions to inline calls to memset. */
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int max_insns_inline_memset;
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/* Bitfield encoding the fuseable pairs of instructions. */
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unsigned int fuseable_ops;
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enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE}
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string_ops_prefer_neon: 1;
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/* Bitfield encoding the fuseable pairs of instructions. Use FUSE_OPS
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in an initializer if multiple fusion operations are supported on a
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target. */
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enum fuse_ops
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{
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FUSE_NOTHING = 0,
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FUSE_MOVW_MOVT = 1 << 0
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} fuseable_ops: 1;
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/* Depth of scheduling queue to check for L2 autoprefetcher. */
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enum arm_sched_autopref sched_autopref;
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/* Issue rate of the processor. */
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unsigned int issue_rate;
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enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL}
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sched_autopref: 2;
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};
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/* Smash multiple fusion operations into a type that can be used for an
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initializer. */
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#define FUSE_OPS(x) ((tune_params::fuse_ops) (x))
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extern const struct tune_params *current_tune;
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extern int vfp3_const_double_for_fract_bits (rtx);
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/* return power of two from operand, otherwise 0. */
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File diff suppressed because it is too large
Load Diff
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@ -2057,10 +2057,11 @@ enum arm_auto_incmodes
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(current_tune->branch_cost (speed_p, predictable_p))
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/* False if short circuit operation is preferred. */
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#define LOGICAL_OP_NON_SHORT_CIRCUIT \
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((optimize_size) \
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? (TARGET_THUMB ? false : true) \
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: (current_tune->logical_op_non_short_circuit[TARGET_ARM]))
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#define LOGICAL_OP_NON_SHORT_CIRCUIT \
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((optimize_size) \
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? (TARGET_THUMB ? false : true) \
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: TARGET_THUMB ? current_tune->logical_op_non_short_circuit_thumb \
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: current_tune->logical_op_non_short_circuit_arm)
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/* Position Independent Code. */
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