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arm-protos.h (arm_sched_autopref): Delete. 

* arm-protos.h (arm_sched_autopref): Delete.
	(tune_params): Re-organize, use enums for flag values.
	(FUSE_OPS): New macro.
	* arm.c (ARM_PREFETCH_NOT_BENEFICIAL): Update.
	(ARM_PREFETCH_BENEFICIAL): Likewise.
	(ARM_FUSE_NOTHING, ARM_FUSE_MOVW_MOVT): Delete.
	(arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune)
	(arm_xscale_tune, arm_9e_tune, arm_marvell_pj4_tune)
	(arm_v6t2_tune, arm_cortex_tune, arm_cortex_a8_tune)
	(arm_cortex_a7_tune, arm_cortex_a15_tune, arm_cortex_a53_tune)
	(arm_cortex_a57_tune,  arm_xgene1_tune, arm_cortex_a5_tune)
	(arm_cortex_a9_tune, arm_cortex_a12_tune, arm_v7m_tune)
	(arm_cortex_m7_tune, arm_v6m_tune, arm_fa726te_tune): Use new
	format.
	(arm_option_override, thumb2_reorg, arm_print_tune_info)
	(aarch_macro_fusion_pair_p): Update uses of current_tune.
	* arm.h (LOGCIAL_OP_NON_SHORT_CIRCUIT): Likewise.

From-SVN: r223090
This commit is contained in:
Richard Earnshaw 2015-05-12 16:39:19 +00:00 committed by Richard Earnshaw
parent cc1e0483ae
commit 52c266bab2
4 changed files with 458 additions and 397 deletions
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20
gcc/ChangeLog
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@ -1,3 +1,23 @@
2015-05-12 Richard Earnshaw <rearnsha@arm.com>
* arm-protos.h (arm_sched_autopref): Delete.
(tune_params): Re-organize, use enums for flag values.
(FUSE_OPS): New macro.
* arm.c (ARM_PREFETCH_NOT_BENEFICIAL): Update.
(ARM_PREFETCH_BENEFICIAL): Likewise.
(ARM_FUSE_NOTHING, ARM_FUSE_MOVW_MOVT): Delete.
(arm_slowmul_tune, arm_fastmul_tune, arm_strongarm_tune)
(arm_xscale_tune, arm_9e_tune, arm_marvell_pj4_tune)
(arm_v6t2_tune, arm_cortex_tune, arm_cortex_a8_tune)
(arm_cortex_a7_tune, arm_cortex_a15_tune, arm_cortex_a53_tune)
(arm_cortex_a57_tune, arm_xgene1_tune, arm_cortex_a5_tune)
(arm_cortex_a9_tune, arm_cortex_a12_tune, arm_v7m_tune)
(arm_cortex_m7_tune, arm_v6m_tune, arm_fa726te_tune): Use new
format.
(arm_option_override, thumb2_reorg, arm_print_tune_info)
(aarch_macro_fusion_pair_p): Update uses of current_tune.
* arm.h (LOGCIAL_OP_NON_SHORT_CIRCUIT): Likewise.
2015-05-12 Sandra Loosemore <sandra@codesourcery.com> 2015-05-12 Sandra Loosemore <sandra@codesourcery.com>
* config/nios2/nios2.md (trap, ctrapsi4): Use "trap" instead of * config/nios2/nios2.md (trap, ctrapsi4): Use "trap" instead of

69
gcc/config/arm/arm-protos.h
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@ -251,13 +251,6 @@ struct cpu_vec_costs {
struct cpu_cost_table; struct cpu_cost_table;
enum arm_sched_autopref
{
ARM_SCHED_AUTOPREF_OFF,
ARM_SCHED_AUTOPREF_RANK,
ARM_SCHED_AUTOPREF_FULL
};
/* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this /* Dump function ARM_PRINT_TUNE_INFO should be updated whenever this
structure is modified. */ structure is modified. */
@ -266,41 +259,57 @@ struct tune_params
bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool); bool (*rtx_costs) (rtx, RTX_CODE, RTX_CODE, int *, bool);
const struct cpu_cost_table *insn_extra_cost; const struct cpu_cost_table *insn_extra_cost;
bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *); bool (*sched_adjust_cost) (rtx_insn *, rtx, rtx_insn *, int *);
int (*branch_cost) (bool, bool);
/* Vectorizer costs. */
const struct cpu_vec_costs* vec_costs;
int constant_limit; int constant_limit;
/* Maximum number of instructions to conditionalise. */ /* Maximum number of instructions to conditionalise. */
int max_insns_skipped; int max_insns_skipped;
int num_prefetch_slots; /* Maximum number of instructions to inline calls to memset. */
int l1_cache_size; int max_insns_inline_memset;
int l1_cache_line_size; /* Issue rate of the processor. */
bool prefer_constant_pool; unsigned int issue_rate;
int (*branch_cost) (bool, bool); /* Explicit prefetch data. */
struct
{
int num_slots;
int l1_cache_size;
int l1_cache_line_size;
} prefetch;
enum {PREF_CONST_POOL_FALSE, PREF_CONST_POOL_TRUE}
prefer_constant_pool: 1;
/* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */ /* Prefer STRD/LDRD instructions over PUSH/POP/LDM/STM. */
bool prefer_ldrd_strd; enum {PREF_LDRD_FALSE, PREF_LDRD_TRUE} prefer_ldrd_strd: 1;
/* The preference for non short cirtcuit operation when optimizing for /* The preference for non short cirtcuit operation when optimizing for
performance. The first element covers Thumb state and the second one performance. The first element covers Thumb state and the second one
is for ARM state. */ is for ARM state. */
bool logical_op_non_short_circuit[2]; enum log_op_non_sc {LOG_OP_NON_SC_FALSE, LOG_OP_NON_SC_TRUE};
/* Vectorizer costs. */ log_op_non_sc logical_op_non_short_circuit_thumb: 1;
const struct cpu_vec_costs* vec_costs; log_op_non_sc logical_op_non_short_circuit_arm: 1;
/* Prefer Neon for 64-bit bitops. */
bool prefer_neon_for_64bits;
/* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */ /* Prefer 32-bit encoding instead of flag-setting 16-bit encoding. */
bool disparage_flag_setting_t16_encodings; enum {DISPARAGE_FLAGS_NEITHER, DISPARAGE_FLAGS_PARTIAL, DISPARAGE_FLAGS_ALL}
/* Prefer 32-bit encoding instead of 16-bit encoding where subset of flags disparage_flag_setting_t16_encodings: 2;
would be set. */ enum {PREF_NEON_64_FALSE, PREF_NEON_64_TRUE} prefer_neon_for_64bits: 1;
bool disparage_partial_flag_setting_t16_encodings;
/* Prefer to inline string operations like memset by using Neon. */ /* Prefer to inline string operations like memset by using Neon. */
bool string_ops_prefer_neon; enum {PREF_NEON_STRINGOPS_FALSE, PREF_NEON_STRINGOPS_TRUE}
/* Maximum number of instructions to inline calls to memset. */ string_ops_prefer_neon: 1;
int max_insns_inline_memset; /* Bitfield encoding the fuseable pairs of instructions. Use FUSE_OPS
/* Bitfield encoding the fuseable pairs of instructions. */ in an initializer if multiple fusion operations are supported on a
unsigned int fuseable_ops; target. */
enum fuse_ops
{
FUSE_NOTHING = 0,
FUSE_MOVW_MOVT = 1 << 0
} fuseable_ops: 1;
/* Depth of scheduling queue to check for L2 autoprefetcher. */ /* Depth of scheduling queue to check for L2 autoprefetcher. */
enum arm_sched_autopref sched_autopref; enum {SCHED_AUTOPREF_OFF, SCHED_AUTOPREF_RANK, SCHED_AUTOPREF_FULL}
/* Issue rate of the processor. */ sched_autopref: 2;
unsigned int issue_rate;
}; };
/* Smash multiple fusion operations into a type that can be used for an
initializer. */
#define FUSE_OPS(x) ((tune_params::fuse_ops) (x))
extern const struct tune_params *current_tune; extern const struct tune_params *current_tune;
extern int vfp3_const_double_for_fract_bits (rtx); extern int vfp3_const_double_for_fract_bits (rtx);
/* return power of two from operand, otherwise 0. */ /* return power of two from operand, otherwise 0. */

757
gcc/config/arm/arm.c
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9
gcc/config/arm/arm.h
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@ -2057,10 +2057,11 @@ enum arm_auto_incmodes
(current_tune->branch_cost (speed_p, predictable_p)) (current_tune->branch_cost (speed_p, predictable_p))
/* False if short circuit operation is preferred. */ /* False if short circuit operation is preferred. */
#define LOGICAL_OP_NON_SHORT_CIRCUIT \ #define LOGICAL_OP_NON_SHORT_CIRCUIT \
((optimize_size) \ ((optimize_size) \
? (TARGET_THUMB ? false : true) \ ? (TARGET_THUMB ? false : true) \
: (current_tune->logical_op_non_short_circuit[TARGET_ARM])) : TARGET_THUMB ? current_tune->logical_op_non_short_circuit_thumb \
: current_tune->logical_op_non_short_circuit_arm)
/* Position Independent Code. */ /* Position Independent Code. */