aarch64: reimplement vqmovn_high* intrinsics using builtins
This patch reimplements the saturating-truncate-and-insert-into-high intrinsics using the appropriate RTL codes and builtins. gcc/ * config/aarch64/aarch64-simd.md (aarch64_<su>qxtn2<mode>_le): Define. (aarch64_<su>qxtn2<mode>_be): Likewise. (aarch64_<su>qxtn2<mode>): Likewise. * config/aarch64/aarch64-simd-builtins.def (sqxtn2, uqxtn2): Define builtins. * config/aarch64/iterators.md (SAT_TRUNC): Define code_iterator. (su): Handle ss_truncate and us_truncate. * config/aarch64/arm_neon.h (vqmovn_high_s16): Reimplement using builtin. (vqmovn_high_s32): Likewise. (vqmovn_high_s64): Likewise. (vqmovn_high_u16): Likewise. (vqmovn_high_u32): Likewise. (vqmovn_high_u64): Likewise. gcc/testsuite/ * gcc.target/aarch64/narrow_high-intrinsics.c: Update uqxtn2 and sqxtn2 scan-assembler-times.
This commit is contained in:
Kyrylo Tkachov
parent
c7f1ff01a2
commit
52cd1cd1b6
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@ -175,6 +175,11 @@
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/* Implemented by aarch64_<sur>qmovn<mode>. */
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BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0, ALL)
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BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0, ALL)
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/* Implemented by aarch64_<su>qxtn2<mode>. */
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BUILTIN_VQN (BINOP, sqxtn2, 0, ALL)
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BUILTIN_VQN (BINOPU, uqxtn2, 0, ALL)
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/* Implemented by aarch64_s<optab><mode>. */
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BUILTIN_VSDQ_I (UNOP, sqabs, 0, ALL)
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BUILTIN_VSDQ_I (UNOP, sqneg, 0, ALL)
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@ -3878,6 +3878,45 @@
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[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
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)
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(define_insn "aarch64_<su>qxtn2<mode>_le"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(match_operand:<VNARROWQ> 1 "register_operand" "0")
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(SAT_TRUNC:<VNARROWQ>
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(match_operand:VQN 2 "register_operand" "w"))))]
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"TARGET_SIMD && !BYTES_BIG_ENDIAN"
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"<su>qxtn2\\t%0.<V2ntype>, %2.<Vtype>"
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[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
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)
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(define_insn "aarch64_<su>qxtn2<mode>_be"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(SAT_TRUNC:<VNARROWQ>
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(match_operand:VQN 2 "register_operand" "w"))
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(match_operand:<VNARROWQ> 1 "register_operand" "0")))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"<su>qxtn2\\t%0.<V2ntype>, %2.<Vtype>"
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[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
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)
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(define_expand "aarch64_<su>qxtn2<mode>"
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[(match_operand:<VNARROWQ2> 0 "register_operand")
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(match_operand:<VNARROWQ> 1 "register_operand")
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(SAT_TRUNC:<VNARROWQ>
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(match_operand:VQN 2 "register_operand"))]
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"TARGET_SIMD"
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{
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_<su>qxtn2<mode>_be (operands[0], operands[1],
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operands[2]));
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else
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emit_insn (gen_aarch64_<su>qxtn2<mode>_le (operands[0], operands[1],
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operands[2]));
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DONE;
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}
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)
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;; <su>q<absneg>
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(define_insn "aarch64_s<optab><mode>"
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@ -9584,72 +9584,42 @@ __extension__ extern __inline int8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vqmovn_high_s16 (int8x8_t __a, int16x8_t __b)
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{
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int8x16_t __result = vcombine_s8 (__a, vcreate_s8 (__AARCH64_UINT64_C (0x0)));
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__asm__ ("sqxtn2 %0.16b, %1.8h"
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: "+w"(__result)
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: "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sqxtn2v8hi (__a, __b);
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}
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__extension__ extern __inline int16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vqmovn_high_s32 (int16x4_t __a, int32x4_t __b)
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{
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int16x8_t __result = vcombine_s16 (__a, vcreate_s16 (__AARCH64_UINT64_C (0x0)));
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__asm__ ("sqxtn2 %0.8h, %1.4s"
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: "+w"(__result)
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: "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sqxtn2v4si (__a, __b);
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}
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vqmovn_high_s64 (int32x2_t __a, int64x2_t __b)
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{
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int32x4_t __result = vcombine_s32 (__a, vcreate_s32 (__AARCH64_UINT64_C (0x0)));
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__asm__ ("sqxtn2 %0.4s, %1.2d"
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: "+w"(__result)
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: "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_sqxtn2v2di (__a, __b);
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}
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__extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vqmovn_high_u16 (uint8x8_t __a, uint16x8_t __b)
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{
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uint8x16_t __result = vcombine_u8 (__a, vcreate_u8 (__AARCH64_UINT64_C (0x0)));
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__asm__ ("uqxtn2 %0.16b, %1.8h"
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: "+w"(__result)
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: "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uqxtn2v8hi_uuu (__a, __b);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vqmovn_high_u32 (uint16x4_t __a, uint32x4_t __b)
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{
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uint16x8_t __result = vcombine_u16 (__a, vcreate_u16 (__AARCH64_UINT64_C (0x0)));
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__asm__ ("uqxtn2 %0.8h, %1.4s"
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: "+w"(__result)
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: "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uqxtn2v4si_uuu (__a, __b);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vqmovn_high_u64 (uint32x2_t __a, uint64x2_t __b)
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{
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uint32x4_t __result = vcombine_u32 (__a, vcreate_u32 (__AARCH64_UINT64_C (0x0)));
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__asm__ ("uqxtn2 %0.4s, %1.2d"
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: "+w"(__result)
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: "w"(__b)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_uqxtn2v2di_uuu (__a, __b);
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}
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__extension__ extern __inline uint8x16_t
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@ -1834,6 +1834,9 @@
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;; Unsigned comparison operators.
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(define_code_iterator FAC_COMPARISONS [lt le ge gt])
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;; Signed and unsigned saturating truncations.
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(define_code_iterator SAT_TRUNC [ss_truncate us_truncate])
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;; SVE integer unary operations.
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(define_code_iterator SVE_INT_UNARY [abs neg not clrsb clz popcount
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(ss_abs "TARGET_SVE2")
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@ -1987,7 +1990,8 @@
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(fix "s") (unsigned_fix "u")
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(div "s") (udiv "u")
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(smax "s") (umax "u")
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(smin "s") (umin "u")])
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(smin "s") (umin "u")
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(ss_truncate "s") (us_truncate "u")])
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;; "s" for signed ops, empty for unsigned ones.
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(define_code_attr s [(sign_extend "s") (zero_extend "")])
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@ -119,7 +119,7 @@ ONE (vmovn_high, uint32x4_t, uint32x2_t, uint64x2_t, u64)
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/* { dg-final { scan-assembler-times "uqshrn2\\tv" 3} } */
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/* { dg-final { scan-assembler-times "sqrshrn2\\tv" 3} } */
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/* { dg-final { scan-assembler-times "uqrshrn2\\tv" 3} } */
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/* { dg-final { scan-assembler-times "uqxtn2 v" 3} } */
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/* { dg-final { scan-assembler-times "sqxtn2 v" 3} } */
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/* { dg-final { scan-assembler-times "uqxtn2\\tv" 3} } */
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/* { dg-final { scan-assembler-times "sqxtn2\\tv" 3} } */
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/* { dg-final { scan-assembler-times "sqxtun2 v" 3} } */
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/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} } */
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