AArch64: Add pattern xtn+xtn2 to uzp1

This turns truncate operations with a hi/lo pair into a single permute of half
the bit size of the input and just ignoring the top bits (which are truncated
out).

i.e.

void d2 (short * restrict a, int *b, int n)
{
    for (int i = 0; i < n; i++)
      a[i] = b[i];
}

now generates:

.L4:
        ldp     q0, q1, [x3]
        add     x3, x3, 32
        uzp1    v0.8h, v0.8h, v1.8h
        str     q0, [x5], 16
        cmp     x4, x3
        bne     .L4

instead of

.L4:
        ldp     q0, q1, [x3]
        add     x3, x3, 32
        xtn     v0.4h, v0.4s
        xtn2    v0.8h, v1.4s
        str     q0, [x5], 16
        cmp     x4, x3
        bne     .L4

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (*aarch64_narrow_trunc<mode>): New.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/narrow_high_combine.c: Update case.
	* gcc.target/aarch64/xtn-combine-1.c: New test.
	* gcc.target/aarch64/xtn-combine-2.c: New test.
	* gcc.target/aarch64/xtn-combine-3.c: New test.
	* gcc.target/aarch64/xtn-combine-4.c: New test.
	* gcc.target/aarch64/xtn-combine-5.c: New test.
	* gcc.target/aarch64/xtn-combine-6.c: New test.

gcc/config/aarch64/aarch64-simd.md

@@ -1753,6 +1753,23 @@
   }
 )
 
+(define_insn "*aarch64_narrow_trunc<mode>"
+  [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
+	(vec_concat:<VNARROWQ2>
+          (truncate:<VNARROWQ>
+            (match_operand:VQN 1 "register_operand" "w"))
+	  (truncate:<VNARROWQ>
+	    (match_operand:VQN 2 "register_operand" "w"))))]
+  "TARGET_SIMD"
+{
+  if (!BYTES_BIG_ENDIAN)
+    return "uzp1\\t%0.<V2ntype>, %1.<V2ntype>, %2.<V2ntype>";
+  else
+    return "uzp1\\t%0.<V2ntype>, %2.<V2ntype>, %1.<V2ntype>";
+}
+  [(set_attr "type" "neon_permute<q>")]
+)
+
 ;; Packing doubles.
 
 (define_expand "vec_pack_trunc_<mode>"

gcc/testsuite/gcc.target/aarch64/narrow_high_combine.c

@@ -225,7 +225,8 @@ TEST_2_UNARY (vqmovun, uint32x4_t, int64x2_t, s64, u32)
 /* { dg-final { scan-assembler-times "\\tuqshrn2\\tv" 6} }  */
 /* { dg-final { scan-assembler-times "\\tsqrshrn2\\tv" 6} }  */
 /* { dg-final { scan-assembler-times "\\tuqrshrn2\\tv" 6} }  */
-/* { dg-final { scan-assembler-times "\\txtn2\\tv" 12} }  */
+/* { dg-final { scan-assembler-times "\\txtn2\\tv" 6} }  */
+/* { dg-final { scan-assembler-times "\\tuzp1\\tv" 6} }  */
 /* { dg-final { scan-assembler-times "\\tuqxtn2\\tv" 6} }  */
 /* { dg-final { scan-assembler-times "\\tsqxtn2\\tv" 6} }  */
 /* { dg-final { scan-assembler-times "\\tsqxtun2\\tv" 6} }  */

gcc/testsuite/gcc.target/aarch64/xtn-combine-1.c

@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN signed
+#define TYPE1 char
+#define TYPE2 short
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+    for (int i = 0; i < n; i++)
+      a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */

gcc/testsuite/gcc.target/aarch64/xtn-combine-2.c

@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN signed
+#define TYPE1 short
+#define TYPE2 int
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+    for (int i = 0; i < n; i++)
+      a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */

gcc/testsuite/gcc.target/aarch64/xtn-combine-3.c

@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN signed
+#define TYPE1 int
+#define TYPE2 long long
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+    for (int i = 0; i < n; i++)
+      a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */

gcc/testsuite/gcc.target/aarch64/xtn-combine-4.c

@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN unsigned
+#define TYPE1 char
+#define TYPE2 short
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+    for (int i = 0; i < n; i++)
+      a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */

gcc/testsuite/gcc.target/aarch64/xtn-combine-5.c

@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN unsigned
+#define TYPE1 short
+#define TYPE2 int
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+    for (int i = 0; i < n; i++)
+      a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */

gcc/testsuite/gcc.target/aarch64/xtn-combine-6.c

@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
+
+#define SIGN unsigned
+#define TYPE1 int
+#define TYPE2 long long
+
+void d2 (SIGN TYPE1 * restrict a, SIGN TYPE2 *b, int n)
+{
+    for (int i = 0; i < n; i++)
+      a[i] = b[i];
+}
+
+/* { dg-final { scan-assembler-times {\tuzp1\t} 1 } } */
+/* { dg-final { scan-assembler-not {\txtn\t} } } */
+/* { dg-final { scan-assembler-not {\txtn2\t} } } */