backport: re PR target/80706 (peephole2 uses uninitialized stack variables on i686)
Backport from mainline 2017-05-11 Uros Bizjak <ubizjak@gmail.com> PR target/80706 * config/i386/sync.md (UNSPEC_LDX_ATOMIC): New unspec. (UNSPEC_STX_ATOMIC): Ditto. (loaddi_via_sse): New insn. (storedi_via_sse): Ditto. (atomic_loaddi_fpu): Emit loaddi_via_sse and storedi_via_sse. Update corresponding peephole2 patterns. (atomic_storedi_fpu): Ditto. testsuite/ChangeLog: Backport from mainline 2017-05-11 Uros Bizjak <ubizjak@gmail.com> Jakub Jelinek <jakub@redhat.com> PR target/80706 * gcc.target/i386/pr80706.c: New test. 2017-05-11 Uros Bizjak <ubizjak@gmail.com> * gcc.target/i386/pr22152.c: Fix undefined testcase. Remove unnecessary loop. Run on 32-bit targets only. From-SVN: r248032
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@ -1,3 +1,17 @@
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2017-05-02 Uros Bizjak <ubizjak@gmail.com>
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Backport from mainline
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2017-05-11 Uros Bizjak <ubizjak@gmail.com>
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PR target/80706
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* config/i386/sync.md (UNSPEC_LDX_ATOMIC): New unspec.
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(UNSPEC_STX_ATOMIC): Ditto.
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(loaddi_via_sse): New insn.
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(storedi_via_sse): Ditto.
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(atomic_loaddi_fpu): Emit loaddi_via_sse and storedi_via_sse.
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Update corresponding peephole2 patterns.
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(atomic_storedi_fpu): Ditto.
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2017-05-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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Backport from mainline
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@ -25,6 +25,9 @@
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UNSPEC_FILD_ATOMIC
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UNSPEC_FIST_ATOMIC
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UNSPEC_LDX_ATOMIC
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UNSPEC_STX_ATOMIC
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;; __atomic support
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UNSPEC_LDA
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UNSPEC_STA
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@ -199,9 +202,8 @@
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}
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else
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{
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adjust_reg_mode (tmp, DImode);
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emit_move_insn (tmp, src);
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emit_move_insn (mem, tmp);
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emit_insn (gen_loaddi_via_sse (tmp, src));
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emit_insn (gen_storedi_via_sse (mem, tmp));
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}
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if (mem != dst)
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@ -226,10 +228,12 @@
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"operands[5] = gen_lowpart (DFmode, operands[1]);")
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(define_peephole2
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[(set (match_operand:DI 0 "sse_reg_operand")
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(match_operand:DI 1 "memory_operand"))
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[(set (match_operand:DF 0 "sse_reg_operand")
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(unspec:DF [(match_operand:DI 1 "memory_operand")]
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UNSPEC_LDX_ATOMIC))
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(set (match_operand:DI 2 "memory_operand")
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(match_dup 0))
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(unspec:DI [(match_dup 0)]
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UNSPEC_STX_ATOMIC))
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(set (match_operand:DF 3 "fp_register_operand")
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(match_operand:DF 4 "memory_operand"))]
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"!TARGET_64BIT
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@ -301,7 +305,9 @@
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rtx dst = operands[0], src = operands[1];
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rtx mem = operands[2], tmp = operands[3];
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if (!SSE_REG_P (src))
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if (SSE_REG_P (src))
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emit_move_insn (dst, src);
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else
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{
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if (REG_P (src))
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{
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@ -313,16 +319,13 @@
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{
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emit_insn (gen_loaddi_via_fpu (tmp, src));
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emit_insn (gen_storedi_via_fpu (dst, tmp));
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DONE;
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}
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else
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{
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adjust_reg_mode (tmp, DImode);
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emit_move_insn (tmp, src);
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src = tmp;
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emit_insn (gen_loaddi_via_sse (tmp, src));
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emit_insn (gen_storedi_via_sse (dst, tmp));
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}
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}
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emit_move_insn (dst, src);
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DONE;
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})
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@ -344,10 +347,12 @@
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(define_peephole2
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[(set (match_operand:DF 0 "memory_operand")
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(match_operand:DF 1 "fp_register_operand"))
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(set (match_operand:DI 2 "sse_reg_operand")
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(match_operand:DI 3 "memory_operand"))
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(set (match_operand:DF 2 "sse_reg_operand")
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(unspec:DF [(match_operand:DI 3 "memory_operand")]
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UNSPEC_LDX_ATOMIC))
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(set (match_operand:DI 4 "memory_operand")
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(match_dup 2))]
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(unspec:DI [(match_dup 2)]
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UNSPEC_STX_ATOMIC))]
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"!TARGET_64BIT
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&& peep2_reg_dead_p (3, operands[2])
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&& rtx_equal_p (operands[0], adjust_address_nv (operands[3], DFmode, 0))"
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@ -382,6 +387,32 @@
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[(set_attr "type" "fmov")
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(set_attr "mode" "DI")])
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(define_insn "loaddi_via_sse"
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[(set (match_operand:DF 0 "register_operand" "=x")
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(unspec:DF [(match_operand:DI 1 "memory_operand" "m")]
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UNSPEC_LDX_ATOMIC))]
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"TARGET_SSE"
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{
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if (TARGET_SSE2)
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return "%vmovq\t{%1, %0|%0, %1}";
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return "movlps\t{%1, %0|%0, %1}";
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}
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[(set_attr "type" "ssemov")
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(set_attr "mode" "DI")])
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(define_insn "storedi_via_sse"
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[(set (match_operand:DI 0 "memory_operand" "=m")
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(unspec:DI [(match_operand:DF 1 "register_operand" "x")]
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UNSPEC_STX_ATOMIC))]
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"TARGET_SSE"
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{
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if (TARGET_SSE2)
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return "%vmovq\t{%1, %0|%0, %1}";
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return "movlps\t{%1, %0|%0, %1}";
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}
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[(set_attr "type" "ssemov")
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(set_attr "mode" "DI")])
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(define_expand "atomic_compare_and_swap<mode>"
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[(match_operand:QI 0 "register_operand") ;; bool success output
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(match_operand:SWI124 1 "register_operand") ;; oldval output
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@ -1,3 +1,17 @@
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2017-05-14 Uros Bizjak <ubizjak@gmail.com>
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Backport from mainline
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2017-05-11 Uros Bizjak <ubizjak@gmail.com>
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Jakub Jelinek <jakub@redhat.com>
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PR target/80706
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* gcc.target/i386/pr80706.c: New test.
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2017-05-11 Uros Bizjak <ubizjak@gmail.com>
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* gcc.target/i386/pr22152.c: Fix undefined testcase.
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Remove unnecessary loop. Run on 32-bit targets only.
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2017-05-13 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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Backport from mainline
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@ -1,18 +1,18 @@
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/* { dg-do compile } */
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/* { dg-do compile { target ia32 } } */
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/* { dg-options "-O2 -msse2 -mtune=core2" } */
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/* { dg-additional-options "-mno-vect8-ret-in-mem" { target *-*-vxworks* } } */
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/* { dg-additional-options "-mabi=sysv" { target x86_64-*-mingw* } } */
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#include <mmintrin.h>
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__m64
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unsigned_add3 (const __m64 * a, const __m64 * b, unsigned int count)
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{
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__m64 sum;
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unsigned int i;
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typedef __SIZE_TYPE__ size_t;
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for (i = 1; i < count; i++)
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sum = _mm_add_si64 (a[i], b[i]);
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__m64
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unsigned_add3 (const __m64 * a, const __m64 * b, size_t count)
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{
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__m64 sum = { 0, 0 };
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if (count > 0)
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sum = _mm_add_si64 (a[count-1], b[count-1]);
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return sum;
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}
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@ -0,0 +1,30 @@
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/* PR target/80706 */
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/* { dg-do run { target sse2_runtime } } */
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/* { dg-options "-O2 -msse2" } */
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union U { double value; struct S { int lsw; int msw; } parts; };
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__attribute__((noinline, noclone)) double
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foo (void)
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{
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__asm volatile ("" : : : "memory");
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return 2.0;
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}
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__attribute__((noinline, noclone)) double
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bar (void)
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{
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double s = foo ();
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union U z;
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z.value = s;
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z.parts.lsw = 0;
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return z.value * z.value + s * s;
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}
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int
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main ()
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{
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if (bar () != 8.0)
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__builtin_abort ();
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return 0;
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}
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