re PR target/80510 (Optimize Power7/power8 Altivec load/stores)
[gcc] 2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/80510 * config/rs6000/predicates.md (simple_offsettable_mem_operand): New predicate. * config/rs6000/rs6000.md (ALTIVEC_DFORM): New iterator. (define_peephole2 for Altivec d-form load): Add peepholes to catch cases where the register allocator uses a move and an offsettable memory operation to/from a FPR register on ISA 2.06/2.07. (define_peephole2 for Altivec d-form store): Likewise. [gcc/testsuite] 2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/80510 * gcc.target/powerpc/pr80510-1.c: New test. * gcc.target/powerpc/pr80510-2.c: Likewise. From-SVN: r248254
This commit is contained in:
Michael Meissner
Michael Meissner
parent
4287da829c
commit
52e14b96bd
@ -1,3 +1,15 @@
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2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/80510
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* config/rs6000/predicates.md (simple_offsettable_mem_operand):
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New predicate.
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* config/rs6000/rs6000.md (ALTIVEC_DFORM): New iterator.
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(define_peephole2 for Altivec d-form load): Add peepholes to catch
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cases where the register allocator uses a move and an offsettable
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memory operation to/from a FPR register on ISA 2.06/2.07.
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(define_peephole2 for Altivec d-form store): Likewise.
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2017-05-18 Uros Bizjak <ubizjak@gmail.com>
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PR target/80799
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@ -847,6 +847,22 @@
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(and (match_operand 0 "memory_operand")
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(match_test "offsettable_nonstrict_memref_p (op)")))
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;; Return 1 if the operand is a simple offsettable memory operand
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;; that does not include pre-increment, post-increment, etc.
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(define_predicate "simple_offsettable_mem_operand"
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(match_operand 0 "offsettable_mem_operand")
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{
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rtx addr = XEXP (op, 0);
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if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
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return 0;
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if (!CONSTANT_P (XEXP (addr, 1)))
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return 0;
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return base_reg_operand (XEXP (addr, 0), Pmode);
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})
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;; Return 1 if the operand is suitable for load/store quad memory.
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;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
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(define_predicate "quad_memory_operand"
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@ -701,6 +701,11 @@
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(define_code_attr SMINMAX [(smin "SMIN")
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(smax "SMAX")])
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;; Iterator to optimize the following cases:
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;; D-form load to FPR register & move to Altivec register
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;; Move Altivec register to FPR register and store
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(define_mode_iterator ALTIVEC_DFORM [DI DF SF])
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;; Start with fixed-point load and store insns. Here we put only the more
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;; complex forms. Basic data transfer is done later.
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@ -14075,6 +14080,82 @@
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[(set_attr "type" "two")
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(set_attr "length" "8")])
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;; Optimize cases where we want to do a D-form load (register+offset) on
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;; ISA 2.06/2.07 to an Altivec register, and the register allocator
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;; has generated:
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;; LFD 0,32(3)
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;; XXLOR 32,0,0
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;;
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;; and we change this to:
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;; LI 0,32
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;; LXSDX 32,3,9
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(define_peephole2
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[(match_scratch:DI 0 "b")
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(set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
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(match_operand:ALTIVEC_DFORM 2 "simple_offsettable_mem_operand"))
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(set (match_operand:ALTIVEC_DFORM 3 "altivec_register_operand")
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(match_dup 1))]
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"TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
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&& !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
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[(set (match_dup 0)
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(match_dup 4))
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(set (match_dup 3)
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(match_dup 5))]
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{
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rtx tmp_reg = operands[0];
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rtx mem = operands[2];
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rtx addr = XEXP (mem, 0);
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rtx add_op0, add_op1, new_addr;
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gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
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add_op0 = XEXP (addr, 0);
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add_op1 = XEXP (addr, 1);
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gcc_assert (REG_P (add_op0));
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new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
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operands[4] = add_op1;
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operands[5] = change_address (mem, <MODE>mode, new_addr);
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})
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;; Optimize cases were want to do a D-form store on ISA 2.06/2.07 from an
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;; Altivec register, and the register allocator has generated:
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;; XXLOR 0,32,32
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;; STFD 0,32(3)
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;;
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;; and we change this to:
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;; LI 0,32
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;; STXSDX 32,3,9
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(define_peephole2
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[(match_scratch:DI 0 "b")
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(set (match_operand:ALTIVEC_DFORM 1 "fpr_reg_operand")
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(match_operand:ALTIVEC_DFORM 2 "altivec_register_operand"))
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(set (match_operand:ALTIVEC_DFORM 3 "simple_offsettable_mem_operand")
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(match_dup 1))]
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"TARGET_VSX && TARGET_POWERPC64 && TARGET_UPPER_REGS_<MODE>
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&& !TARGET_P9_DFORM_SCALAR && peep2_reg_dead_p (2, operands[1])"
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[(set (match_dup 0)
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(match_dup 4))
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(set (match_dup 5)
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(match_dup 2))]
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{
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rtx tmp_reg = operands[0];
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rtx mem = operands[3];
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rtx addr = XEXP (mem, 0);
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rtx add_op0, add_op1, new_addr;
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gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
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add_op0 = XEXP (addr, 0);
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add_op1 = XEXP (addr, 1);
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gcc_assert (REG_P (add_op0));
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new_addr = gen_rtx_PLUS (DImode, add_op0, tmp_reg);
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operands[4] = add_op1;
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operands[5] = change_address (mem, <MODE>mode, new_addr);
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})
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;; Miscellaneous ISA 2.06 (power7) instructions
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(define_insn "addg6s"
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@ -1,3 +1,9 @@
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2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/80510
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* gcc.target/powerpc/pr80510-1.c: New test.
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* gcc.target/powerpc/pr80510-2.c: Likewise.
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2017-05-18 Eric Gallager <egall@gwmail.gwu.edu>
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* gcc.dg/pragma-diag-7.c: New test.
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211
gcc/testsuite/gcc.target/powerpc/pr80510-1.c
Normal file
211
gcc/testsuite/gcc.target/powerpc/pr80510-1.c
Normal file
@ -0,0 +1,211 @@
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */
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/* { dg-options "-mcpu=power7 -O2" } */
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/* Make sure that STXSDX is generated for double scalars in Altivec registers
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on power7 instead of moving the value to a FPR register and doing a X-FORM
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store. */
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#ifndef TYPE
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#define TYPE double
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#endif
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#ifndef TYPE_IN
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#define TYPE_IN TYPE
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#endif
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#ifndef TYPE_OUT
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#define TYPE_OUT TYPE
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#endif
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#ifndef ITYPE
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#define ITYPE long
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#endif
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#ifdef DO_CALL
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extern ITYPE get_bits (ITYPE);
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#else
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#define get_bits(X) (X)
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#endif
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void test (ITYPE *bits, ITYPE n, TYPE one, TYPE_IN *p, TYPE_OUT *q)
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{
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TYPE x_00 = p[ 0];
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TYPE x_01 = p[ 1];
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TYPE x_02 = p[ 2];
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TYPE x_03 = p[ 3];
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TYPE x_04 = p[ 4];
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TYPE x_05 = p[ 5];
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TYPE x_06 = p[ 6];
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TYPE x_07 = p[ 7];
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TYPE x_08 = p[ 8];
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TYPE x_09 = p[ 9];
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TYPE x_10 = p[10];
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TYPE x_11 = p[11];
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TYPE x_12 = p[12];
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TYPE x_13 = p[13];
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TYPE x_14 = p[14];
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TYPE x_15 = p[15];
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TYPE x_16 = p[16];
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TYPE x_17 = p[17];
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TYPE x_18 = p[18];
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TYPE x_19 = p[19];
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TYPE x_20 = p[20];
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TYPE x_21 = p[21];
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TYPE x_22 = p[22];
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TYPE x_23 = p[23];
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TYPE x_24 = p[24];
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TYPE x_25 = p[25];
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TYPE x_26 = p[26];
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TYPE x_27 = p[27];
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TYPE x_28 = p[28];
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TYPE x_29 = p[29];
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TYPE x_30 = p[30];
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TYPE x_31 = p[31];
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TYPE x_32 = p[32];
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TYPE x_33 = p[33];
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TYPE x_34 = p[34];
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TYPE x_35 = p[35];
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TYPE x_36 = p[36];
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TYPE x_37 = p[37];
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TYPE x_38 = p[38];
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TYPE x_39 = p[39];
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TYPE x_40 = p[40];
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TYPE x_41 = p[41];
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TYPE x_42 = p[42];
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TYPE x_43 = p[43];
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TYPE x_44 = p[44];
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TYPE x_45 = p[45];
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TYPE x_46 = p[46];
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TYPE x_47 = p[47];
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TYPE x_48 = p[48];
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TYPE x_49 = p[49];
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ITYPE i;
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for (i = 0; i < n; i++)
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{
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ITYPE bit = get_bits (bits[i]);
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if ((bit & ((ITYPE)1) << 0) != 0) x_00 += one;
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if ((bit & ((ITYPE)1) << 1) != 0) x_01 += one;
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if ((bit & ((ITYPE)1) << 2) != 0) x_02 += one;
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if ((bit & ((ITYPE)1) << 3) != 0) x_03 += one;
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if ((bit & ((ITYPE)1) << 4) != 0) x_04 += one;
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if ((bit & ((ITYPE)1) << 5) != 0) x_05 += one;
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if ((bit & ((ITYPE)1) << 6) != 0) x_06 += one;
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if ((bit & ((ITYPE)1) << 7) != 0) x_07 += one;
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if ((bit & ((ITYPE)1) << 8) != 0) x_08 += one;
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if ((bit & ((ITYPE)1) << 9) != 0) x_09 += one;
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if ((bit & ((ITYPE)1) << 10) != 0) x_10 += one;
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if ((bit & ((ITYPE)1) << 11) != 0) x_11 += one;
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if ((bit & ((ITYPE)1) << 12) != 0) x_12 += one;
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if ((bit & ((ITYPE)1) << 13) != 0) x_13 += one;
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if ((bit & ((ITYPE)1) << 14) != 0) x_14 += one;
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if ((bit & ((ITYPE)1) << 15) != 0) x_15 += one;
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if ((bit & ((ITYPE)1) << 16) != 0) x_16 += one;
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if ((bit & ((ITYPE)1) << 17) != 0) x_17 += one;
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if ((bit & ((ITYPE)1) << 18) != 0) x_18 += one;
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if ((bit & ((ITYPE)1) << 19) != 0) x_19 += one;
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if ((bit & ((ITYPE)1) << 20) != 0) x_20 += one;
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if ((bit & ((ITYPE)1) << 21) != 0) x_21 += one;
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if ((bit & ((ITYPE)1) << 22) != 0) x_22 += one;
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if ((bit & ((ITYPE)1) << 23) != 0) x_23 += one;
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if ((bit & ((ITYPE)1) << 24) != 0) x_24 += one;
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if ((bit & ((ITYPE)1) << 25) != 0) x_25 += one;
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if ((bit & ((ITYPE)1) << 26) != 0) x_26 += one;
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if ((bit & ((ITYPE)1) << 27) != 0) x_27 += one;
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if ((bit & ((ITYPE)1) << 28) != 0) x_28 += one;
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if ((bit & ((ITYPE)1) << 29) != 0) x_29 += one;
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if ((bit & ((ITYPE)1) << 30) != 0) x_30 += one;
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if ((bit & ((ITYPE)1) << 31) != 0) x_31 += one;
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if ((bit & ((ITYPE)1) << 32) != 0) x_32 += one;
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if ((bit & ((ITYPE)1) << 33) != 0) x_33 += one;
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if ((bit & ((ITYPE)1) << 34) != 0) x_34 += one;
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if ((bit & ((ITYPE)1) << 35) != 0) x_35 += one;
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if ((bit & ((ITYPE)1) << 36) != 0) x_36 += one;
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if ((bit & ((ITYPE)1) << 37) != 0) x_37 += one;
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if ((bit & ((ITYPE)1) << 38) != 0) x_38 += one;
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if ((bit & ((ITYPE)1) << 39) != 0) x_39 += one;
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if ((bit & ((ITYPE)1) << 40) != 0) x_40 += one;
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if ((bit & ((ITYPE)1) << 41) != 0) x_41 += one;
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if ((bit & ((ITYPE)1) << 42) != 0) x_42 += one;
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if ((bit & ((ITYPE)1) << 43) != 0) x_43 += one;
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if ((bit & ((ITYPE)1) << 44) != 0) x_44 += one;
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if ((bit & ((ITYPE)1) << 45) != 0) x_45 += one;
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if ((bit & ((ITYPE)1) << 46) != 0) x_46 += one;
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if ((bit & ((ITYPE)1) << 47) != 0) x_47 += one;
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if ((bit & ((ITYPE)1) << 48) != 0) x_48 += one;
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if ((bit & ((ITYPE)1) << 49) != 0) x_49 += one;
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}
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q[ 0] = x_00;
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q[ 1] = x_01;
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q[ 2] = x_02;
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q[ 3] = x_03;
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q[ 4] = x_04;
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q[ 5] = x_05;
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q[ 6] = x_06;
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q[ 7] = x_07;
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q[ 8] = x_08;
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q[ 9] = x_09;
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q[10] = x_10;
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q[11] = x_11;
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q[12] = x_12;
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q[13] = x_13;
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q[14] = x_14;
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q[15] = x_15;
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q[16] = x_16;
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q[17] = x_17;
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q[18] = x_18;
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q[19] = x_19;
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q[20] = x_20;
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q[21] = x_21;
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q[22] = x_22;
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q[23] = x_23;
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q[24] = x_24;
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q[25] = x_25;
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q[26] = x_26;
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q[27] = x_27;
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q[28] = x_28;
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q[29] = x_29;
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q[30] = x_30;
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q[31] = x_31;
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q[32] = x_32;
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q[33] = x_33;
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q[34] = x_34;
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q[35] = x_35;
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q[36] = x_36;
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q[37] = x_37;
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q[38] = x_38;
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q[39] = x_39;
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q[40] = x_40;
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q[41] = x_41;
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q[42] = x_42;
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q[43] = x_43;
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q[44] = x_44;
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q[45] = x_45;
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q[46] = x_46;
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q[47] = x_47;
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q[48] = x_48;
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q[49] = x_49;
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}
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/* { dg-final { scan-assembler {\mxsadddp\M} } } */
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/* { dg-final { scan-assembler {\mstxsdx\M} } } */
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/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
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212
gcc/testsuite/gcc.target/powerpc/pr80510-2.c
Normal file
212
gcc/testsuite/gcc.target/powerpc/pr80510-2.c
Normal file
@ -0,0 +1,212 @@
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/* { dg-do compile { target { powerpc*-*-* } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_p8vector_ok } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
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/* { dg-options "-mcpu=power8 -O2" } */
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/* Make sure that STXSSPX is generated for float scalars in Altivec registers
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on power7 instead of moving the value to a FPR register and doing a X-FORM
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store. */
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#ifndef TYPE
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#define TYPE float
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#endif
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#ifndef TYPE_IN
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#define TYPE_IN TYPE
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#endif
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#ifndef TYPE_OUT
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#define TYPE_OUT TYPE
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#endif
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#ifndef ITYPE
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#define ITYPE long
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#endif
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#ifdef DO_CALL
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extern ITYPE get_bits (ITYPE);
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#else
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#define get_bits(X) (X)
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#endif
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void test (ITYPE *bits, ITYPE n, TYPE one, TYPE_IN *p, TYPE_OUT *q)
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{
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TYPE x_00 = p[ 0];
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TYPE x_01 = p[ 1];
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TYPE x_02 = p[ 2];
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TYPE x_03 = p[ 3];
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TYPE x_04 = p[ 4];
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||||
TYPE x_05 = p[ 5];
|
||||
TYPE x_06 = p[ 6];
|
||||
TYPE x_07 = p[ 7];
|
||||
TYPE x_08 = p[ 8];
|
||||
TYPE x_09 = p[ 9];
|
||||
|
||||
TYPE x_10 = p[10];
|
||||
TYPE x_11 = p[11];
|
||||
TYPE x_12 = p[12];
|
||||
TYPE x_13 = p[13];
|
||||
TYPE x_14 = p[14];
|
||||
TYPE x_15 = p[15];
|
||||
TYPE x_16 = p[16];
|
||||
TYPE x_17 = p[17];
|
||||
TYPE x_18 = p[18];
|
||||
TYPE x_19 = p[19];
|
||||
|
||||
TYPE x_20 = p[20];
|
||||
TYPE x_21 = p[21];
|
||||
TYPE x_22 = p[22];
|
||||
TYPE x_23 = p[23];
|
||||
TYPE x_24 = p[24];
|
||||
TYPE x_25 = p[25];
|
||||
TYPE x_26 = p[26];
|
||||
TYPE x_27 = p[27];
|
||||
TYPE x_28 = p[28];
|
||||
TYPE x_29 = p[29];
|
||||
|
||||
TYPE x_30 = p[30];
|
||||
TYPE x_31 = p[31];
|
||||
TYPE x_32 = p[32];
|
||||
TYPE x_33 = p[33];
|
||||
TYPE x_34 = p[34];
|
||||
TYPE x_35 = p[35];
|
||||
TYPE x_36 = p[36];
|
||||
TYPE x_37 = p[37];
|
||||
TYPE x_38 = p[38];
|
||||
TYPE x_39 = p[39];
|
||||
|
||||
TYPE x_40 = p[40];
|
||||
TYPE x_41 = p[41];
|
||||
TYPE x_42 = p[42];
|
||||
TYPE x_43 = p[43];
|
||||
TYPE x_44 = p[44];
|
||||
TYPE x_45 = p[45];
|
||||
TYPE x_46 = p[46];
|
||||
TYPE x_47 = p[47];
|
||||
TYPE x_48 = p[48];
|
||||
TYPE x_49 = p[49];
|
||||
|
||||
ITYPE i;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
{
|
||||
ITYPE bit = get_bits (bits[i]);
|
||||
|
||||
if ((bit & ((ITYPE)1) << 0) != 0) x_00 += one;
|
||||
if ((bit & ((ITYPE)1) << 1) != 0) x_01 += one;
|
||||
if ((bit & ((ITYPE)1) << 2) != 0) x_02 += one;
|
||||
if ((bit & ((ITYPE)1) << 3) != 0) x_03 += one;
|
||||
if ((bit & ((ITYPE)1) << 4) != 0) x_04 += one;
|
||||
if ((bit & ((ITYPE)1) << 5) != 0) x_05 += one;
|
||||
if ((bit & ((ITYPE)1) << 6) != 0) x_06 += one;
|
||||
if ((bit & ((ITYPE)1) << 7) != 0) x_07 += one;
|
||||
if ((bit & ((ITYPE)1) << 8) != 0) x_08 += one;
|
||||
if ((bit & ((ITYPE)1) << 9) != 0) x_09 += one;
|
||||
|
||||
if ((bit & ((ITYPE)1) << 10) != 0) x_10 += one;
|
||||
if ((bit & ((ITYPE)1) << 11) != 0) x_11 += one;
|
||||
if ((bit & ((ITYPE)1) << 12) != 0) x_12 += one;
|
||||
if ((bit & ((ITYPE)1) << 13) != 0) x_13 += one;
|
||||
if ((bit & ((ITYPE)1) << 14) != 0) x_14 += one;
|
||||
if ((bit & ((ITYPE)1) << 15) != 0) x_15 += one;
|
||||
if ((bit & ((ITYPE)1) << 16) != 0) x_16 += one;
|
||||
if ((bit & ((ITYPE)1) << 17) != 0) x_17 += one;
|
||||
if ((bit & ((ITYPE)1) << 18) != 0) x_18 += one;
|
||||
if ((bit & ((ITYPE)1) << 19) != 0) x_19 += one;
|
||||
|
||||
if ((bit & ((ITYPE)1) << 20) != 0) x_20 += one;
|
||||
if ((bit & ((ITYPE)1) << 21) != 0) x_21 += one;
|
||||
if ((bit & ((ITYPE)1) << 22) != 0) x_22 += one;
|
||||
if ((bit & ((ITYPE)1) << 23) != 0) x_23 += one;
|
||||
if ((bit & ((ITYPE)1) << 24) != 0) x_24 += one;
|
||||
if ((bit & ((ITYPE)1) << 25) != 0) x_25 += one;
|
||||
if ((bit & ((ITYPE)1) << 26) != 0) x_26 += one;
|
||||
if ((bit & ((ITYPE)1) << 27) != 0) x_27 += one;
|
||||
if ((bit & ((ITYPE)1) << 28) != 0) x_28 += one;
|
||||
if ((bit & ((ITYPE)1) << 29) != 0) x_29 += one;
|
||||
|
||||
if ((bit & ((ITYPE)1) << 30) != 0) x_30 += one;
|
||||
if ((bit & ((ITYPE)1) << 31) != 0) x_31 += one;
|
||||
if ((bit & ((ITYPE)1) << 32) != 0) x_32 += one;
|
||||
if ((bit & ((ITYPE)1) << 33) != 0) x_33 += one;
|
||||
if ((bit & ((ITYPE)1) << 34) != 0) x_34 += one;
|
||||
if ((bit & ((ITYPE)1) << 35) != 0) x_35 += one;
|
||||
if ((bit & ((ITYPE)1) << 36) != 0) x_36 += one;
|
||||
if ((bit & ((ITYPE)1) << 37) != 0) x_37 += one;
|
||||
if ((bit & ((ITYPE)1) << 38) != 0) x_38 += one;
|
||||
if ((bit & ((ITYPE)1) << 39) != 0) x_39 += one;
|
||||
|
||||
if ((bit & ((ITYPE)1) << 40) != 0) x_40 += one;
|
||||
if ((bit & ((ITYPE)1) << 41) != 0) x_41 += one;
|
||||
if ((bit & ((ITYPE)1) << 42) != 0) x_42 += one;
|
||||
if ((bit & ((ITYPE)1) << 43) != 0) x_43 += one;
|
||||
if ((bit & ((ITYPE)1) << 44) != 0) x_44 += one;
|
||||
if ((bit & ((ITYPE)1) << 45) != 0) x_45 += one;
|
||||
if ((bit & ((ITYPE)1) << 46) != 0) x_46 += one;
|
||||
if ((bit & ((ITYPE)1) << 47) != 0) x_47 += one;
|
||||
if ((bit & ((ITYPE)1) << 48) != 0) x_48 += one;
|
||||
if ((bit & ((ITYPE)1) << 49) != 0) x_49 += one;
|
||||
}
|
||||
|
||||
q[ 0] = x_00;
|
||||
q[ 1] = x_01;
|
||||
q[ 2] = x_02;
|
||||
q[ 3] = x_03;
|
||||
q[ 4] = x_04;
|
||||
q[ 5] = x_05;
|
||||
q[ 6] = x_06;
|
||||
q[ 7] = x_07;
|
||||
q[ 8] = x_08;
|
||||
q[ 9] = x_09;
|
||||
|
||||
q[10] = x_10;
|
||||
q[11] = x_11;
|
||||
q[12] = x_12;
|
||||
q[13] = x_13;
|
||||
q[14] = x_14;
|
||||
q[15] = x_15;
|
||||
q[16] = x_16;
|
||||
q[17] = x_17;
|
||||
q[18] = x_18;
|
||||
q[19] = x_19;
|
||||
|
||||
q[20] = x_20;
|
||||
q[21] = x_21;
|
||||
q[22] = x_22;
|
||||
q[23] = x_23;
|
||||
q[24] = x_24;
|
||||
q[25] = x_25;
|
||||
q[26] = x_26;
|
||||
q[27] = x_27;
|
||||
q[28] = x_28;
|
||||
q[29] = x_29;
|
||||
|
||||
q[30] = x_30;
|
||||
q[31] = x_31;
|
||||
q[32] = x_32;
|
||||
q[33] = x_33;
|
||||
q[34] = x_34;
|
||||
q[35] = x_35;
|
||||
q[36] = x_36;
|
||||
q[37] = x_37;
|
||||
q[38] = x_38;
|
||||
q[39] = x_39;
|
||||
|
||||
q[40] = x_40;
|
||||
q[41] = x_41;
|
||||
q[42] = x_42;
|
||||
q[43] = x_43;
|
||||
q[44] = x_44;
|
||||
q[45] = x_45;
|
||||
q[46] = x_46;
|
||||
q[47] = x_47;
|
||||
q[48] = x_48;
|
||||
q[49] = x_49;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler {\mxsaddsp\M} } } */
|
||||
/* { dg-final { scan-assembler {\mstxsspx\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */
|
||||
/* { dg-final { scan-assembler-not {\mmfvsrwz\M} } } */
|
||||
Loading…
Reference in New Issue
Block a user