Correct errors in comments.
(calc_live_regs, expand_acall): Delete TARGET_SMALLCALL support. (need_slot): Add comment. Delete test of INSN_ANNULLED_BRANCH_P. (print_operand_address): Delete '*', '^', '!' support. (synth_constant): Call zero_extend* instead of and*. Call ashlsi3_k instead of ashlsi3_n. (prepare_scc_operands): Abort for NE case. (output_move_double, output_far_jump, output_branch): Delete commented out code. Don't output assembler comments. (gen_ashift): Don't call addsi3. (fixit): Delete redundant test for QImode constants. (hi_const): Delete TARGET_SHORTADDR support. (find_barrier): Don't put constant pool between mova and its label. (add_function, seen_function, bsr_operand, mac_operand, fake_shift): Delete. (sh_expand_prologue, expand_acall): Delete TARGET_BSR support. (general_movsrc_operand): Don't reject non-I CONST_INT. From-SVN: r8889
This commit is contained in:
Jim Wilson
parent
51bd623f2b
commit
5325c0fa57
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@ -201,8 +201,8 @@ push_regs (mask)
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/* Print an instruction which would have gone into a delay slot after
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an instructiuon, but couldn't because the instruction expanded into a
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sequence where putting the slot insn at the end wouldn't work. */
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another instruction, but couldn't because the other instruction expanded
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into a sequence where putting the slot insn at the end wouldn't work. */
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static void
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print_slot (insn)
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@ -248,13 +248,6 @@ calc_live_regs (count_ptr)
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count++;
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}
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}
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else if (TARGET_SMALLCALL)
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{
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/* Don't need to push anthing, but count the regs which have
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been pushed by the wrapper */
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if (call_used_regs[reg])
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count++;
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}
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else
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{
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/* Only push those regs which are used and need to be saved */
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@ -271,12 +264,16 @@ calc_live_regs (count_ptr)
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return live_regs_mask;
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}
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/* This returns true if INSN is a conditional branch whose delay slot
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has been filled. This indicates that it must be a bf.s/bt.s.
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??? This function could be eliminated. */
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static int
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need_slot (insn)
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rtx insn;
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{
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return (insn && !INSN_ANNULLED_BRANCH_P (XVECEXP (insn, 0, 0)));
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return insn;
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}
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/* Print the operand address in x to the stream */
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@ -343,9 +340,6 @@ print_operand_address (stream, x)
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according to modifier code.
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'.' print a .s if insn needs delay slot
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'*' print a local label
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'^' increment the local label number
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'!' dump the constant table
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'#' output a nop if there is nothing to put in the delay slot
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'@' print rte or rts depending upon pragma interruptness
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'R' print the LSW of a dp value - changes if in little endian
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@ -367,12 +361,6 @@ print_operand (stream, x, code)
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if (need_slot (final_sequence))
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fprintf (stream, ".s");
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break;
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case '*':
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fprintf (stream, "LF%d", lf);
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break;
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case '^':
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lf++;
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break;
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case '@':
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if (pragma_interrupt)
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fprintf (stream, "rte");
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@ -488,6 +476,9 @@ sextb (x)
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00000000 00000000 00000000 1NNNNNNNN load and zero extend byte
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00000000 00000000 11111111 1NNNNNNNN load and zero extend word
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??? Can add cases using swap.b and swap.w.
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Can add cases using andi to get `1s 1s 1s 0NNNNNN1'.
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Can add many more cases for TARGET_CLEN3, but doubt their usefulness.
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*/
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@ -521,13 +512,13 @@ synth_constant (operands, mode)
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if ((i & 0xffffff80) == 0x0000ff80)
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{
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emit_move_insn (dst, GEN_INT (sextb (i)));
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emit_insn (gen_and_ffff (dst, dst));
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emit_insn (gen_zero_extendhisi2 (dst, gen_lowpart (HImode, dst)));
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}
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/* 00000000 00000000 00000000 1NNNNNNNN load and zero extend byte */
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else if ((i & 0xffffff80) == 0x00000080)
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{
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emit_move_insn (dst, GEN_INT (sextb (i)));
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emit_insn (gen_and_ff (dst, dst));
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emit_insn (gen_zero_extendqisi2 (dst, gen_lowpart (QImode, dst)));
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}
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/* 00000000 00000000 00000000 NNNNNNNN0 load and shift by 1
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11111111 11111111 11111111 NNNNNNNN0 load and shift by 1 */
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@ -535,7 +526,7 @@ synth_constant (operands, mode)
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|| (i & 0xffffff01) == 0xffffff00)
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{
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emit_move_insn (dst, GEN_INT (sextb (i >> 1)));
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emit_insn (gen_ashlsi3_n (dst, dst, GEN_INT (1)));
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emit_insn (gen_ashlsi3_k (dst, dst, GEN_INT (1)));
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}
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/* 00000000 00000000 0000000N NNNNNNN00 load and shift by 2
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11111111 11111111 1111111N NNNNNNN00 load and shift by 2*/
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@ -543,7 +534,7 @@ synth_constant (operands, mode)
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|| (i & 0xfffffe03) == 0xfffffe00)
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{
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emit_move_insn (dst, GEN_INT (sextb (i >> 2)));
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emit_insn (gen_ashlsi3_n (dst, dst, GEN_INT (2)));
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emit_insn (gen_ashlsi3_k (dst, dst, GEN_INT (2)));
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}
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/* 00000000 00000000 0NNNNNNN 000000000 load and shift by 8
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11111111 11111111 1NNNNNNN 000000000 load and shift by 8 */
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@ -552,7 +543,7 @@ synth_constant (operands, mode)
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|| (i & 0xffff80ff) == 0xffff8000)
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{
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emit_move_insn (dst, GEN_INT (sextb (i >> 8)));
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emit_insn (gen_ashlsi3_n (dst, dst, GEN_INT (8)));
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emit_insn (gen_ashlsi3_k (dst, dst, GEN_INT (8)));
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}
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/* 00000000 0NNNNNNN 00000000 000000000 load and shift by 16
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11111111 1NNNNNNN 00000000 000000000 load and shift by 16 */
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@ -560,13 +551,13 @@ synth_constant (operands, mode)
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|| (i & 0xff80ffff) == 0xff800000)
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{
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emit_move_insn (dst, GEN_INT (sextb (i >> 16)));
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emit_insn (gen_ashlsi3_n (dst, dst, GEN_INT (16)));
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emit_insn (gen_ashlsi3_k (dst, dst, GEN_INT (16)));
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}
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/* 00000000 00000000 0NNNNNNN 0NNNNNNNN load shift 8 and add */
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else if ((i & 0xffff8080) == 0 && TARGET_CLEN3)
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{
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emit_move_insn (dst, GEN_INT (sextb (i >> 8)));
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emit_insn (gen_ashlsi3_n (dst, dst, GEN_INT (8)));
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emit_insn (gen_ashlsi3_k (dst, dst, GEN_INT (8)));
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emit_insn (gen_addsi3 (dst, dst, GEN_INT (i & 0x7f)));
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}
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else
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@ -808,8 +799,8 @@ prepare_scc_operands (code)
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switch (code)
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{
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case NE:
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newcode = EQ;
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break;
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/* It isn't possible to handle this case. */
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abort ();
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case LT:
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newcode = GT;
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break;
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@ -861,8 +852,6 @@ output_movedouble (insn, operands, mode)
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rtx dst = operands[0];
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rtx src = operands[1];
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/* fprintf (asm_out_file, "! move double \n");
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fprintf (asm_out_file, "! pc %04x\n", insn_addresses[INSN_UID (insn)]);*/
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if (GET_CODE (dst) == MEM
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&& GET_CODE (XEXP (dst, 0)) == POST_INC)
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{
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@ -881,9 +870,9 @@ output_movedouble (insn, operands, mode)
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*/
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if (REGNO (src) + 1 == REGNO (dst))
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return "mov %T1,%T0\n\tmov %1,%0 ! cra";
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return "mov %T1,%T0\n\tmov %1,%0";
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else
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return "mov %1,%0\n\tmov %T1,%T0 ! crb";
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return "mov %1,%0\n\tmov %T1,%T0";
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}
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else if (GET_CODE (src) == CONST_INT)
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{
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@ -929,7 +918,7 @@ output_movedouble (insn, operands, mode)
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}
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else if (GET_CODE (inside) == POST_INC)
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{
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return "mov.l %1,%0\n\tmov.l %1,%T0 !mdi\n";
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return "mov.l %1,%0\n\tmov.l %1,%T0";
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}
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else
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abort ();
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@ -942,7 +931,7 @@ output_movedouble (insn, operands, mode)
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{
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/* This move clobbers both index registers,
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calculate the sum in one register. */
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fprintf (asm_out_file, " add %s,%s ! special fix\n",
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fprintf (asm_out_file, " add %s,%s\n",
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reg_names[ptrreg2], reg_names[ptrreg1]);
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if (dreg == ptrreg1)
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@ -976,7 +965,7 @@ output_movedouble (insn, operands, mode)
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if (dreg == ptrreg1)
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{
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/* Copy into the second half first */
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return "mov.l %T1,%T0\n\tmov.l %1,%0 ! cr";
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return "mov.l %T1,%T0\n\tmov.l %1,%0";
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}
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}
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@ -1114,14 +1103,14 @@ output_far_jump (insn, op)
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output_asm_insn ("mov.l %1,@-r15", vec);
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output_asm_insn ("mov.l %O0,%1", vec);
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output_asm_insn ("jmp @%1 ! 32 xcond", vec);
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output_asm_insn ("jmp @%1", vec);
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output_asm_insn ("mov.l @r15+,%1", vec);
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}
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else
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{
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output_asm_insn ("mov.l r13,@-r15", 0);
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output_asm_insn ("mov.l %O0,r13", &thislab);
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output_asm_insn ("jmp @r13 ! 32 zcond", 0);
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output_asm_insn ("jmp @r13", 0);
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output_asm_insn ("mov.l @r15+,r13", 0);
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}
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@ -1139,8 +1128,6 @@ output_branch (logic, insn)
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extern rtx recog_operand[];
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int label = lf++;
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/* fprintf (asm_out_file, "! pc %04x\n", insn_addresses[INSN_UID (insn)]);*/
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switch (get_attr_length (insn))
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{
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case 2:
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@ -1172,7 +1159,7 @@ output_branch (logic, insn)
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}
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recog_operand[0] = oldop;
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output_asm_insn ("bra %l0 ! 12 bit cond ", recog_operand);
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output_asm_insn ("bra %l0", recog_operand);
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fprintf (asm_out_file, "\tor r0,r0\n");
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fprintf (asm_out_file, "LF%d:\n", label);
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}
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@ -1330,11 +1317,6 @@ final_prescan_insn (insn, opvec, noperands)
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}
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}
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/* Stuff taken from m88k.c */
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/* Output to FILE the start of the assembler file. */
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struct option
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@ -1582,10 +1564,7 @@ gen_ashift (type, n, reg)
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emit_insn (gen_lshrsi3_k (reg, reg, GEN_INT (n)));
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break;
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case ASHIFT:
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if (n == 1)
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emit_insn (gen_addsi3 (reg, reg, reg));
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else
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emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
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emit_insn (gen_ashlsi3_k (reg, reg, GEN_INT (n)));
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break;
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}
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}
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@ -1809,15 +1788,9 @@ fixit (src, mode)
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return 1;
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}
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if (GET_CODE (src) == LABEL_REF)
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{
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return 1;
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}
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return 1;
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if (GET_CODE (src) == CONST_INT)
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{
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/* All QI insns are ok */
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if (mode == QImode)
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return 1;
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/* The rest may need to be fixed */
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return !CONST_OK_FOR_I (INTVAL (src));
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}
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return 0;
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@ -1834,10 +1807,6 @@ hi_const (src)
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&& GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF)
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return 1;
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if (TARGET_SHORTADDR
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&& GET_CODE (src) == SYMBOL_REF)
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return 1;
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return (GET_CODE (src) == CONST_INT
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&& INTVAL (src) >= -32768
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&& INTVAL (src) <= 32767);
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@ -1846,6 +1815,14 @@ hi_const (src)
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/* Find the last barrier less than MAX_COUNT bytes from FROM, or create one.
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If an HI move is found, then make sure that MAX_COUNT_HI isn't broken from that one. */
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/* ??? It would be good to put constant pool tables between a case jump and
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the jump table. This fails for two reasons. First, there is no
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barrier after the case jump. This is a bug in the casesi pattern.
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Second, inserting the table here may break the mova instruction that
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loads the jump table address, by moving the jump table too far away.
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We fix that problem by never outputting the constant pool between a mova
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and its label. */
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static
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rtx
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find_barrier (from)
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@ -1856,6 +1833,7 @@ find_barrier (from)
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int found_hi = 0;
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int found_si = 0;
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rtx found_barrier = 0;
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rtx found_mova = 0;
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while (from
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&& count_si < max_count_si
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&& count_hi < max_count_hi)
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@ -1885,6 +1863,18 @@ find_barrier (from)
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{
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inc = get_attr_length (from);
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}
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/* ??? This isn't correct anymore. The mova RTL has changed. */
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if (GET_CODE (from) == INSN
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&& GET_CODE (PATTERN (from)) == SET
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&& GET_CODE (SET_DEST (PATTERN (from))) == REG
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&& GET_CODE (SET_SRC (PATTERN (from))) == LABEL_REF)
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found_mova = from;
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else if (GET_CODE (from) == JUMP_INSN
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&& (GET_CODE (PATTERN (from)) == ADDR_VEC
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|| GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC))
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found_mova = 0;
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if (found_si)
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count_si += inc;
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if (found_hi)
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@ -1892,6 +1882,11 @@ find_barrier (from)
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from = NEXT_INSN (from);
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}
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/* Insert the constant pool table before the mova instruction, to prevent
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the mova label reference from going out of range. */
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if (found_mova)
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from = found_mova;
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if (!found_barrier)
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{
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/* We didn't find a barrier in time to
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@ -2036,41 +2031,6 @@ equality_operator (x, mode)
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return (code == EQ || code == NE);
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}
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/* Add this function to the list of ones seen - temporary
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gross hack to try out bsrs. */
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struct flist
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{
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char *name;
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struct flist *next;
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};
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struct flist *head;
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static void
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add_function (name)
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char *name;
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{
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struct flist *n = (struct flist *) xmalloc (sizeof (struct flist));
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int l = strlen (name) + 1;
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n->name = xmalloc (l);
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memcpy (n->name, name, l);
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n->next = head;
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head = n;
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}
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static int
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seen_function (name)
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char *name;
|
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{
|
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struct flist *p = head;
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for (p = head; p; p = p->next)
|
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{
|
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if (strcmp (p->name, name) == 0)
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return 1;
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}
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return 0;
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}
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/* Framefull frame looks like:
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arg-5
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@ -2090,10 +2050,6 @@ seen_function (name)
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local-1
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local-0 <- fp points here
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If TARGET_SMALLCALL, then the preserved registers are pushed by a
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wrapper before the routine is entered, so the regs are always pushed
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and there are two pr's on the stack - the caller and the wrapper.
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*/
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|
|
@ -2137,10 +2093,6 @@ sh_expand_prologue ()
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{
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emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
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}
|
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if (TARGET_BSR)
|
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{
|
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add_function (IDENTIFIER_POINTER (DECL_NAME (current_function_decl)));
|
||||
}
|
||||
|
||||
/* ??? Hack. Clear out the table set up by gen_shifty_op since this
|
||||
info does not apply to the next function. */
|
||||
|
|
@ -2245,10 +2197,7 @@ handle_pragma (file)
|
|||
|
||||
/* insn expand helpers */
|
||||
|
||||
/* Emit insns to perform a call.
|
||||
If TARGET_SHORTADDR then use a bsr. If TARGET_SMALLCALL, then load the
|
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target address into r1 and call __saveargs, otherwise
|
||||
perform the standard call sequence */
|
||||
/* Emit insns to perform a call. */
|
||||
|
||||
void
|
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expand_acall (isa_retval, operands)
|
||||
|
|
@ -2260,29 +2209,13 @@ expand_acall (isa_retval, operands)
|
|||
rtx call_target = operands[isa_retval + 0];
|
||||
rtx numargs = operands[isa_retval + 1];
|
||||
|
||||
if (TARGET_BSR && bsr_operand (call_target, VOIDmode))
|
||||
if (GET_CODE (call_target) == MEM)
|
||||
{
|
||||
call = gen_rtx (CALL, VOIDmode, call_target, numargs);
|
||||
call_target = force_reg (Pmode, XEXP (call_target, 0));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GET_CODE (call_target) == MEM)
|
||||
{
|
||||
call_target = force_reg (Pmode,
|
||||
XEXP (call_target, 0));
|
||||
}
|
||||
if (TARGET_SMALLCALL)
|
||||
{
|
||||
rtx tmp = gen_reg_rtx (SImode);
|
||||
rtx r1 = gen_rtx (REG, SImode, 1);
|
||||
emit_move_insn (tmp, gen_rtx (SYMBOL_REF, SImode, "__saveargs"));
|
||||
emit_move_insn (r1, call_target);
|
||||
emit_insn (gen_rtx (USE, VOIDmode, r1));
|
||||
call_target = tmp;
|
||||
}
|
||||
|
||||
call = gen_rtx (CALL, VOIDmode, gen_rtx (MEM, SImode, call_target), numargs);
|
||||
}
|
||||
call = gen_rtx (CALL, VOIDmode, gen_rtx (MEM, SImode, call_target), numargs);
|
||||
|
||||
if (isa_retval)
|
||||
{
|
||||
call = gen_rtx (SET, VOIDmode, ret, call);
|
||||
|
|
@ -2345,11 +2278,6 @@ general_movsrc_operand (op, mode)
|
|||
&& system_reg_operand (XEXP (op, 0), mode)))
|
||||
return 0;
|
||||
|
||||
if (GET_CODE (op) == CONST_INT)
|
||||
{
|
||||
int i = INTVAL (op);
|
||||
return CONST_OK_FOR_I (i);
|
||||
}
|
||||
return general_operand (op, mode);
|
||||
}
|
||||
|
||||
|
|
@ -2379,26 +2307,6 @@ general_movdst_operand (op, mode)
|
|||
|
||||
|
||||
|
||||
/* Returns 1 if OP is valid destination for a bsr. */
|
||||
|
||||
int
|
||||
bsr_operand (op, mode)
|
||||
rtx op;
|
||||
enum machine_mode mode;
|
||||
{
|
||||
if (TARGET_BSR)
|
||||
{
|
||||
if (GET_CODE (op) == SYMBOL_REF)
|
||||
{
|
||||
if (!strcmp (XSTR (op, 0),
|
||||
IDENTIFIER_POINTER (DECL_NAME (current_function_decl))))
|
||||
return 1;
|
||||
return (seen_function (XSTR (op, 0)));
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Returns 1 if OP is an immediate ok for a byte index. */
|
||||
|
||||
int
|
||||
|
|
@ -2539,25 +2447,6 @@ logical_operand (op, mode)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* Returns 1 if OP is a valid operand for a MAC instruction,
|
||||
either a register or indirect memory. For now we don't
|
||||
try and recognise a mac insn */
|
||||
|
||||
int
|
||||
mac_operand (op, mode)
|
||||
rtx op;
|
||||
enum machine_mode mode;
|
||||
{
|
||||
if (arith_reg_operand (op, mode))
|
||||
return 1;
|
||||
#if 0
|
||||
Turned off till mac is understood
|
||||
if (GET_CODE (op) == MEM)
|
||||
return 1;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Determine where to put an argument to a function.
|
||||
Value is zero to push the argument on the stack,
|
||||
or a hard register in which to store the argument.
|
||||
|
|
@ -2619,17 +2508,3 @@ sh_function_arg_partial_nregs (CUM, MODE, TYPE, NAMED)
|
|||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* Turn this on to recognise shift insns which aren't supported in the
|
||||
hardware. This will allow the combiner to notice more patterns,
|
||||
but the down side is that the asm outputter will have to emit
|
||||
several instructions for each shift which isn't possible in the
|
||||
hardware, this makes scheduling perform badly .*/
|
||||
|
||||
int fake_shift()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue