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aarch64: Remove early clobber from ATOMIC_LDOP scratch

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* config/aarch64/atomics.md (aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse):
	The scratch register need not be early-clobber.  Document the reason
	why we cannot use ST<OP>.

From-SVN: r265703
This commit is contained in:
Richard Henderson 2018-10-31 23:11:22 +00:00 committed by Richard Henderson
parent 4911c15c97
commit 53de1ea800
2 changed files with 19 additions and 1 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2018-10-31 Richard Henderson <richard.henderson@linaro.org>
* config/aarch64/atomics.md (aarch64_atomic_<ATOMIC_LDOP><ALLI>_lse):
scratch register need not be early-clobber. Document the reason
why we cannot use ST<OP>.
2018-10-31 Joseph Myers <joseph@codesourcery.com>
PR bootstrap/82856

14
gcc/config/aarch64/atomics.md
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@ -263,6 +263,18 @@
}
)
;; It is tempting to want to use ST<OP> for relaxed and release
;; memory models here. However, that is incompatible with the
;; C++ memory model for the following case:
;;
;; atomic_fetch_add(ptr, 1, memory_order_relaxed);
;; atomic_thread_fence(memory_order_acquire);
;;
;; The problem is that the architecture says that ST<OP> (and LD<OP>
;; insns where the destination is XZR) are not regarded as a read.
;; However we also implement the acquire memory barrier with DMB LD,
;; and so the ST<OP> is not blocked by the barrier.
(define_insn "aarch64_atomic_<atomic_ldoptab><mode>_lse"
[(set (match_operand:ALLI 0 "aarch64_sync_memory_operand" "+Q")
(unspec_volatile:ALLI
@ -270,7 +282,7 @@
(match_operand:ALLI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand")]
ATOMIC_LDOP))
(clobber (match_scratch:ALLI 3 "=&r"))]
(clobber (match_scratch:ALLI 3 "=r"))]
"TARGET_LSE"
{
enum memmodel model = memmodel_from_int (INTVAL (operands[2]));