re PR target/49868 (Implement named address space to place/access data in flash memory)
PR target/49868 PR target/50887 * doc/extend.texi (Named Address Spaces): Split into subsections. (AVR Named Address Spaces): New subsection. (M32C Named Address Spaces): New subsection. (RL78 Named Address Spaces): New subsection. (SPU Named Address Spaces): New subsection. (Variable Attributes): New anchor "AVR Variable Attributes". (AVR Variable Attributes): Rewrite and avoid wording "address space" in this context. * doc/invoke.texi (AVR Options): Rewrite and add documentation for -maccumulate-args, -mbranch-cost=, -mrelax, -mshort-calls. (AVR Built-in Macros): New subsubsection therein. * doc/md.texi (AVR constraints): Remove "C04", "R". From-SVN: r183336
This commit is contained in:
Georg-Johann Lay
Georg-Johann Lay
parent
8ecd1c0da4
commit
542bf446b9
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@ -1,3 +1,20 @@
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2012-01-20 Georg-Johann Lay <avr@gjlay.de>
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PR target/49868
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PR target/50887
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* doc/extend.texi (Named Address Spaces): Split into subsections.
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(AVR Named Address Spaces): New subsection.
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(M32C Named Address Spaces): New subsection.
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(RL78 Named Address Spaces): New subsection.
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(SPU Named Address Spaces): New subsection.
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(Variable Attributes): New anchor "AVR Variable Attributes".
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(AVR Variable Attributes): Rewrite and avoid wording
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"address space" in this context.
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* doc/invoke.texi (AVR Options): Rewrite and add documentation
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for -maccumulate-args, -mbranch-cost=, -mrelax, -mshort-calls.
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(AVR Built-in Macros): New subsubsection therein.
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* doc/md.texi (AVR constraints): Remove "C04", "R".
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2012-01-20 Richard Guenther <rguenther@suse.de>
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PR tree-optimization/51903
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@ -1215,15 +1215,207 @@ Pragmas to control overflow and rounding behaviors are not implemented.
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Fixed-point types are supported by the DWARF2 debug information format.
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@node Named Address Spaces
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@section Named address spaces
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@cindex named address spaces
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@section Named Address Spaces
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@cindex Named Address Spaces
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As an extension, the GNU C compiler supports named address spaces as
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defined in the N1275 draft of ISO/IEC DTR 18037. Support for named
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address spaces in GCC will evolve as the draft technical report
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changes. Calling conventions for any target might also change. At
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present, only the SPU, M32C, and RL78 targets support other address
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spaces. On the SPU target, for example, variables may be declared as
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present, only the AVR, SPU, M32C, and RL78 targets support address
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spaces other than the generic address space.
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Address space identifiers may be used exactly like any other C type
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qualifier (e.g., @code{const} or @code{volatile}). See the N1275
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document for more details.
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@anchor{AVR Named Address Spaces}
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@subsection AVR Named Address Spaces
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On the AVR target, there are several address spaces that can be used
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in order to put read-only data into the flash memory and access that
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data by means of the special instructions @code{LPM} or @code{ELPM}
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needed to read from flash.
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Per default, any data including read-only data is located in RAM so
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that address spaces are needed to locate read-only data in flash memory
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@emph{and} to generate the right instructions to access the data
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without using (inline) assembler code.
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@table @code
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@item __pgm
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@cindex @code{__pgm} AVR Named Address Spaces
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The @code{__pgm} qualifier will locate data in the
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@code{.progmem.data} section. Data will be read using the @code{LPM}
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instruction. Pointers to this address space are 16 bits wide.
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@item __pgm1
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@item __pgm2
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@item __pgm3
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@item __pgm4
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@item __pgm5
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@cindex @code{__pgm1} AVR Named Address Spaces
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@cindex @code{__pgm2} AVR Named Address Spaces
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@cindex @code{__pgm3} AVR Named Address Spaces
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@cindex @code{__pgm4} AVR Named Address Spaces
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@cindex @code{__pgm5} AVR Named Address Spaces
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These are 16-bit address spaces locating data in section
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@code{.progmem@var{N}.data} where @var{N} refers to
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address space @code{__pgm@var{N}}.
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The compiler will set the @code{RAMPZ} segment register approptiately
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before reading data by means of the @code{ELPM} instruction.
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On devices with less 64kiB flash segments as indicated by the address
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space, the compiler will cut down the segment number to a number the
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device actually supports. Counting starts at @code{0}
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for space @code{__pgm}. For example, if you access address space
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@code{__pgm3} on an ATmega128 device with two 64@tie{}kiB flash segments,
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the compiler will generate a read from @code{__pgm1}, i.e.@: it
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will load @code{RAMPZ} with@tie{}@code{1} before reading.
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@item __pgmx
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@cindex @code{__pgmx} AVR Named Address Spaces
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This is a 24-bit address space that linearizes flash and RAM:
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If the high bit of the address is set, data is read from
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RAM using the lower two bytes as RAM address.
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If the high bit of the address is clear, data is read from flash
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with @code{RAMPZ} set according to the high byte of the address.
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Objects in this address space will be located in @code{.progmem.data}.
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@end table
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For each named address space supported by avr-gcc there is an equally
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named but uppercase built-in macro defined.
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The purpose is to facilitate testing if respective address space
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support is available or not:
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@example
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#ifdef __PGM
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const __pgm int var = 1;
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int read_i (void)
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@{
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return i;
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@}
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#else
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#include <avr/pgmspace.h> /* From avr-libc */
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const int var PROGMEM = 1;
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int read_i (void)
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@{
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return (int) pgm_read_word (&i);
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@}
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#endif /* __PGM */
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@end example
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Notice that attribute @ref{AVR Variable Attributes,@code{progmem}}
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locates data in flash but
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accesses to these data will be to generic address space, i.e.@: RAM,
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so that you need special access functions like @code{pgm_read_byte}
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from @w{@uref{http://nongnu.org/avr-libc/user-manual,avr-libc}}.
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@b{Limitations and caveats}
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@itemize
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@item
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Reading across the 64@tie{}KiB section boundary of
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the @code{__pgm} or @code{__pgm@var{N}} address spaces
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will show undefined behaviour. The only address space that
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supports reading across the 64@tie{}KiB flash segment boundaries is
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@code{__pgmx}.
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@item
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If you use one if the @code{__pgm@var{N}} address spaces
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you will have to arrange your linker skript to locate the
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@code{.progmem@var{N}.data} sections according to your needs.
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@item
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Any data or pointers to the AVR address spaces spaces must
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also be qualified as @code{const}, i.e.@: as read-only data.
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This still applies if the data in one of these address
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spaces like software version number or lookup tables are intended to
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be changed after load time by, say, a boot loader. In this case
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the right qualification is @code{const} @code{volatile} so that the compiler
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must not optimize away known values or insert them
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as immediates into operands of instructions.
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@item
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Code like the following is not yet supported because of missing
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support in avr-binutils,
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see @w{@uref{http://sourceware.org/PR13503,PR13503}}.
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@example
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extern const __pgmx char foo;
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const __pgmx void *pfoo = &foo;
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@end example
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The code will throw an assembler warning and the high byte of
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@code{pfoo} will be initialized with @code{0}, i.e.@: the
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initialization will be as if @code{foo} was located in the first
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64@tie{}KiB chunk of flash.
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@item
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Address arithmetic for the @code{__pgmx} address space is carried out
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as 16-bit signed integer arithmetic. This means that in the following
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code array positions with offsets @code{idx}@tie{}>@tie{}8191 are
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inaccessible.
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@example
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extern const __pgmx long lookup[];
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long read_lookup (unsigned idx)
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@{
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return lookup[idx];
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@}
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@end example
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@end itemize
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@b{Example}
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@example
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char my_read (const __pgm ** p)
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@{
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/* p is a pointer to RAM that points to a pointer to flash.
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The first indirection of p will read that flash pointer
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from RAM and the second indirection reads a char from this
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flash address. */
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return **p;
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@}
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/* Locate array[] in flash memory */
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const __pgm int array[] = @{ 3, 5, 7, 11, 13, 17, 19 @};
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int i = 1;
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int main (void)
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@{
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/* Return 17 by reading from flash memory */
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return array[array[i]];
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@}
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@end example
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@subsection M32C Named Address Spaces
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@cindex @code{__far} M32C Named Address Spaces
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On the M32C target, with the R8C and M16C cpu variants, variables
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qualified with @code{__far} are accessed using 32-bit addresses in
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order to access memory beyond the first 64@tie{}Ki bytes. If
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@code{__far} is used with the M32CM or M32C cpu variants, it has no
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effect.
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@subsection RL78 Named Address Spaces
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@cindex @code{__far} RL78 Named Address Spaces
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On the RL78 target, variables qualified with @code{__far} are accessed
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with 32-bit pointers (20-bit addresses) rather than the default 16-bit
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addresses. Non-far variables are assumed to appear in the topmost
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64@tie{}KiB of the address space.
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@subsection SPU Named Address Spaces
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@cindex @code{__ea} SPU Named Address Spaces
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On the SPU target variables may be declared as
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belonging to another address space by qualifying the type with the
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@code{__ea} address space identifier:
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@ -1236,20 +1428,6 @@ special code to access this variable. It may use runtime library
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support, or generate special machine instructions to access that address
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space.
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The @code{__ea} identifier may be used exactly like any other C type
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qualifier (e.g., @code{const} or @code{volatile}). See the N1275
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document for more details.
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On the M32C target, with the R8C and M16C cpu variants, variables
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qualified with @code{__far} are accessed using 32-bit addresses in
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order to access memory beyond the first 64k bytes. If @code{__far} is
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used with the M32CM or M32C cpu variants, it has no effect.
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On the RL78 target, variables qualified with @code{__far} are accessed
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with 32-bit pointers (20-bit addresses) rather than the default 16-bit
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addresses. Non-far variables are assumed to appear in the topmost 64
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kB of the address space.
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@node Zero Length
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@section Arrays of Length Zero
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@cindex arrays of length zero
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@ -4563,17 +4741,24 @@ The @code{dllexport} attribute is described in @ref{Function Attributes}.
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@end table
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@anchor{AVR Variable Attributes}
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@subsection AVR Variable Attributes
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@table @code
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@item progmem
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@cindex @code{progmem} AVR variable attribute
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The @code{progmem} attribute is used on the AVR to place data in the program
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memory address space (flash). This is accomplished by putting
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respective variables into a section whose name starts with @code{.progmem}.
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The @code{progmem} attribute is used on the AVR to place read-only
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data in the non-volatile program memory (flash). The @code{progmem}
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attribute accomplishes this by putting respective variables into a
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section whose name starts with @code{.progmem}.
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AVR is a Harvard architecture processor and data and reas only data
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normally resides in the data memory address space (RAM).
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This attrubute wirks similar to the @code{section} attribute
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but adds additional checking. Notice that just like the
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@code{section} attribute, @code{progmem} affects the location
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of the data but not how this data is accessed.
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AVR is a Harvard architecture processor and data and read-only data
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normally resides in the data memory (RAM).
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@end table
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@subsection Blackfin Variable Attributes
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@ -495,8 +495,9 @@ Objective-C and Objective-C++ Dialects}.
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-mfix-cortex-m3-ldrd}
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@emph{AVR Options}
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@gccoptlist{-mmcu=@var{mcu} -mno-interrupts @gol
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-mcall-prologues -mtiny-stack -mint8 -mstrict-X}
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@gccoptlist{-mmcu=@var{mcu} -maccumulate-args -mbranch-cost=@var{cost} @gol
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-mcall-prologues -mint8 -mno-interrupts -mrelax -mshort-calls @gol
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-mstrict-X -mtiny-stack}
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@emph{Blackfin Options}
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@gccoptlist{-mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]} @gol
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@ -10897,41 +10898,99 @@ These options are defined for AVR implementations:
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@table @gcctabopt
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@item -mmcu=@var{mcu}
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@opindex mmcu
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Specify ATMEL AVR instruction set or MCU type.
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Specify Atmel AVR instruction set architectures (ISA) or MCU type.
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Instruction set avr1 is for the minimal AVR core, not supported by the C
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compiler, only for assembler programs (MCU types: at90s1200, attiny10,
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attiny11, attiny12, attiny15, attiny28).
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For a complete list of @var{mcu} values that are supported by avr-gcc,
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see the compiler output when called with the @code{--help=target}
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command line option.
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The default for this option is@tie{}@code{avr2}.
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Instruction set avr2 (default) is for the classic AVR core with up to
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8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
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at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
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at90c8534, at90s8535).
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avr-gcc supports the following AVR devices and ISAs:
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Instruction set avr3 is for the classic AVR core with up to 128K program
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memory space (MCU types: atmega103, atmega603, at43usb320, at76c711).
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@table @code
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Instruction set avr4 is for the enhanced AVR core with up to 8K program
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memory space (MCU types: atmega8, atmega83, atmega85).
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@item avr1
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This ISA is implemented by the minimal AVR core and supported
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for assembler only.
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@*@var{mcu}@tie{}= @code{at90s1200},
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@code{attiny10}, @code{attiny11}, @code{attiny12}, @code{attiny15},
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@code{attiny28}.
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Instruction set avr5 is for the enhanced AVR core with up to 128K program
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memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
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atmega64, atmega128, at43usb355, at94k).
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@item avr2
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``Classic'' devices with up to 8@tie{}KiB of program memory.
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@*@var{mcu}@tie{}= @code{at90s2313}, @code{attiny26}, @code{at90c8534},
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@dots{}
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@item -mno-interrupts
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@opindex mno-interrupts
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Generated code is not compatible with hardware interrupts.
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Code size will be smaller.
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@item avr25
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``Classic'' devices with up to 8@tie{}KiB of program memory and with
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the @code{MOVW} instruction.
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@*@var{mcu}@tie{}= @code{attiny2313}, @code{attiny261}, @code{attiny24},
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@dots{}
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@item avr3
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``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
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@*@var{mcu}@tie{}= @code{at43usb355}, @code{at76c711}.
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@item avr31
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``Classic'' devices with 128@tie{}KiB of program memory.
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@*@var{mcu}@tie{}= @code{atmega103}, @code{at43usb320}.
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@item avr35
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``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program
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memory and with the @code{MOVW} instruction.
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@*@var{mcu}@tie{}= @code{at90usb162}, @code{atmega8u2},
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@code{attiny167}, @dots{}
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@item avr4
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``Enhanced'' devices with up to 8@tie{}KiB of program memory.
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@*@var{mcu}@tie{}= @code{atmega8}, @code{atmega88}, @code{at90pwm81},
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@dots{}
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@item avr5
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``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory.
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@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega6490}, @code{at90can64},
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@dots{}
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@item avr51
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``Enhanced'' devices with 128@tie{}KiB of program memory.
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@*@var{mcu}@tie{}= @code{atmega128}, @code{at90can128}, @code{at90usb1287},
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@dots{}
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@item avr6
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``Enhanced'' devices with 3-byte PC, i.e.@: with at least 256@tie{}KiB
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of program memory.
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@*@var{mcu}@tie{}= @code{atmega2560}, @code{atmega2561}.
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@end table
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@item -maccumulate-args
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@opindex maccumulate-args
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Accumulate outgoing function arguments and acquire/release the needed
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stack space for outgoing function arguments once in function
|
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prologue/epilogue. Without this option, outgoing arguments are pushed
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before calling a function and popped afterwards.
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Popping the arguments after the function call can be expensive on
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AVR so that accumulating the stack space might lead to smaller
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executables because areguments need not to be removed from the
|
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stack after such a function call.
|
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|
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This option can lead to reduced code size for functions that get
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their arguments on the stack like functions that perform several
|
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calls to printf-like functions.
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@item -mbranch-cost=@var{cost}
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@opindex mbranch-cost
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Set the branch costs for conditional branch instructions to
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@var{cost}. Reasonable values for @var{cost} are small, non-negative
|
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integers. The default branch cost is 0.
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@item -mcall-prologues
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@opindex mcall-prologues
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Functions prologues/epilogues expanded as call to appropriate
|
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subroutines. Code size will be smaller.
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@item -mtiny-stack
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||||
@opindex mtiny-stack
|
||||
Change only the low 8 bits of the stack pointer.
|
||||
|
||||
@item -mint8
|
||||
@opindex mint8
|
||||
Assume int to be 8 bit integer. This affects the sizes of all types: A
|
||||
|
|
@ -10940,9 +10999,33 @@ and long long will be 4 bytes. Please note that this option does not
|
|||
comply to the C standards, but it will provide you with smaller code
|
||||
size.
|
||||
|
||||
@item -mno-interrupts
|
||||
@opindex mno-interrupts
|
||||
Generated code is not compatible with hardware interrupts.
|
||||
Code size will be smaller.
|
||||
|
||||
@item -mrelax
|
||||
@opindex mrelax
|
||||
Try to replace @code{CALL} resp.@: @code{JMP} instruction by the shorter
|
||||
@code{RCALL} resp.@: @code{RJMP} instruction if applicable.
|
||||
Setting @code{-mrelax} just adds the @code{--relax} option to the
|
||||
linker command line when the linker is called.
|
||||
|
||||
Jump relaxing is performed by the linker because jump offsets are not
|
||||
known before code is located. Therefore, the assembler code generated by the
|
||||
compiler will be the same, but the instructions in the executable may
|
||||
differ from instructions in the assembler code.
|
||||
|
||||
@item -mshort-calls
|
||||
@opindex mshort-calls
|
||||
Use @code{RCALL}/@code{RJMP} instructions even on devices with
|
||||
16@tie{}KiB or more of program memory, i.e.@: on devices that
|
||||
have the @code{CALL} and @code{JMP} instructions.
|
||||
See also the @code{-mrelax} command line option.
|
||||
|
||||
@item -mstrict-X
|
||||
@opindex mstrict-X
|
||||
Use register @code{X} in a way proposed by the hardware. This means
|
||||
Use address register @code{X} in a way proposed by the hardware. This means
|
||||
that @code{X} will only be used in indirect, post-increment or
|
||||
pre-decrement addressing.
|
||||
|
||||
|
|
@ -10950,28 +11033,35 @@ Without this option, the @code{X} register may be used in the same way
|
|||
as @code{Y} or @code{Z} which then is emulated by additional
|
||||
instructions.
|
||||
For example, loading a value with @code{X+const} addressing with a
|
||||
small @code{const <= 63} to a register @var{Rn} will be printed as
|
||||
small non-negative @code{const < 64} to a register @var{Rn} will be
|
||||
performed as
|
||||
|
||||
@example
|
||||
adiw r26, const
|
||||
ld @var{Rn}, X
|
||||
sbiw r26, const
|
||||
adiw r26, const ; X += const
|
||||
ld @var{Rn}, X ; @var{Rn} = *X
|
||||
sbiw r26, const ; X -= const
|
||||
@end example
|
||||
|
||||
@item -mtiny-stack
|
||||
@opindex mtiny-stack
|
||||
Only use the lower 8@tie{}bits of the stack pointer and assume that the high
|
||||
byte of SP is always zero.
|
||||
@end table
|
||||
|
||||
@subsubsection @code{EIND} and Devices with more than 128k Bytes of Flash
|
||||
@subsubsection @code{EIND} and Devices with more than 128 Ki Bytes of Flash
|
||||
|
||||
Pointers in the implementation are 16 bits wide.
|
||||
Pointers in the implementation are 16@tie{}bits wide.
|
||||
The address of a function or label is represented as word address so
|
||||
that indirect jumps and calls can address any code address in the
|
||||
range of 64k words.
|
||||
that indirect jumps and calls can target any code address in the
|
||||
range of 64@tie{}Ki words.
|
||||
|
||||
In order to faciliate indirect jump on devices with more than 128k
|
||||
In order to facilitate indirect jump on devices with more than 128@tie{}Ki
|
||||
bytes of program memory space, there is a special function register called
|
||||
@code{EIND} that serves as most significant part of the target address
|
||||
when @code{EICALL} or @code{EIJMP} instructions are used.
|
||||
|
||||
Indirect jumps and calls on these devices are handled as follows and
|
||||
are subject to some limitations:
|
||||
Indirect jumps and calls on these devices are handled as follows by
|
||||
the compiler and are subject to some limitations:
|
||||
|
||||
@itemize @bullet
|
||||
|
||||
|
|
@ -10986,19 +11076,20 @@ For the impact of avr-libc on @code{EIND}, see the
|
|||
|
||||
@item
|
||||
The compiler uses @code{EIND} implicitely in @code{EICALL}/@code{EIJMP}
|
||||
instructions or might read @code{EIND} directly.
|
||||
instructions or might read @code{EIND} directly in order to emulate an
|
||||
indirect call/jump by means of a @code{RET} instruction.
|
||||
|
||||
@item
|
||||
The compiler assumes that @code{EIND} never changes during the startup
|
||||
code or run of the application. In particular, @code{EIND} is not
|
||||
code or during the application. In particular, @code{EIND} is not
|
||||
saved/restored in function or interrupt service routine
|
||||
prologue/epilogue.
|
||||
|
||||
@item
|
||||
It is legitimate for user-specific startup code to set up @code{EIND}
|
||||
early, for example by means of initialization code located in
|
||||
section @code{.init3}, and thus prior to general startup code that
|
||||
initializes RAM and calls constructors.
|
||||
section @code{.init3}. Such code runs prior to general startup code
|
||||
that initializes RAM and calls constructors.
|
||||
|
||||
@item
|
||||
For indirect calls to functions and computed goto, the linker will
|
||||
|
|
@ -11053,7 +11144,8 @@ int main (void)
|
|||
@}
|
||||
@end example
|
||||
|
||||
Instead, a stub has to be set up:
|
||||
Instead, a stub has to be set up, i.e.@: the function has to be called
|
||||
through a symbol (@code{func_4} in the example):
|
||||
|
||||
@example
|
||||
int main (void)
|
||||
|
|
@ -11069,6 +11161,92 @@ and the application be linked with @code{-Wl,--defsym,func_4=0x4}.
|
|||
Alternatively, @code{func_4} can be defined in the linker script.
|
||||
@end itemize
|
||||
|
||||
@subsubsection AVR Built-in Macros
|
||||
|
||||
avr-gcc defines several built-in macros so that the user code can test
|
||||
for presence of absence of features. Almost any of the following
|
||||
built-in macros are deduced from device capabilities and thus
|
||||
triggered by the @code{-mmcu=} command line option.
|
||||
|
||||
For even more AVR-specific built-in macros see
|
||||
@ref{AVR Named Address Spaces} and @ref{AVR Built-in Functions}.
|
||||
|
||||
@table @code
|
||||
|
||||
@item __AVR_@var{Device}__
|
||||
Setting @code{-mmcu=@var{device}} defines this built-in macro that reflects
|
||||
the device's name. For example, @code{-mmcu=atmega8} will define the
|
||||
built-in macro @code{__AVR_ATmega8__}, @code{-mmcu=attiny261a} defines
|
||||
@code{__AVR_ATtiny261A__}, etc.
|
||||
|
||||
The built-in macros' names follow
|
||||
the scheme @code{__AVR_@var{Device}__} where @var{Device} is
|
||||
the device name as from the AVR user manual. The difference between
|
||||
@var{Device} in the built-in macro and @var{device} in
|
||||
@code{-mmcu=@var{device}} is that the latter is always lower case.
|
||||
|
||||
@item __AVR_HAVE_RAMPZ__
|
||||
@item __AVR_HAVE_ELPM__
|
||||
The device has the @code{RAMPZ} special function register and thus the
|
||||
@code{ELPM} instruction.
|
||||
|
||||
@item __AVR_HAVE_ELPMX__
|
||||
The device has the @code{ELPM R@var{n},Z} and @code{ELPM
|
||||
R@var{n},Z+} instructions.
|
||||
|
||||
@item __AVR_HAVE_MOVW__
|
||||
The device has the @code{MOVW} instruction to perform 16-bit
|
||||
register-register moves.
|
||||
|
||||
@item __AVR_HAVE_LPMX__
|
||||
The device has the @code{LPM R@var{n},Z} and @code{LPM
|
||||
R@var{n},Z+} instructions.
|
||||
|
||||
@item __AVR_HAVE_MUL__
|
||||
The device has a hardware multiplier.
|
||||
|
||||
@item __AVR_HAVE_JMP_CALL__
|
||||
The device has the @code{JMP} and @code{CALL} instructions.
|
||||
This is the case for devices with at least 16@tie{}KiB of program
|
||||
memory and if @code{-mshort-calls} is not set.
|
||||
|
||||
@item __AVR_HAVE_EIJMP_EICALL__
|
||||
@item __AVR_3_BYTE_PC__
|
||||
The device has the @code{EIJMP} and @code{EICALL} instructions.
|
||||
This is the case for devices with at least 256@tie{}KiB of program memory.
|
||||
This also means that the program counter
|
||||
(PC) is 3@tie{}bytes wide.
|
||||
|
||||
@item __AVR_2_BYTE_PC__
|
||||
The program counter (PC) is 2@tie{}bytes wide. This is the case for devices
|
||||
with up to 128@tie{}KiB of program memory.
|
||||
|
||||
@item __AVR_HAVE_8BIT_SP__
|
||||
@item __AVR_HAVE_16BIT_SP__
|
||||
The stack pointer (SP) is 8@tie{}bits resp. 16@tie{}bits wide.
|
||||
The definition of these macros is affected by @code{-mtiny-stack}.
|
||||
|
||||
@item __NO_INTERRUPTS__
|
||||
This macro reflects the @code{-mno-interrupts} command line option.
|
||||
|
||||
@item __AVR_ERRATA_SKIP__
|
||||
@item __AVR_ERRATA_SKIP_JMP_CALL__
|
||||
Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit
|
||||
instructions because of a hardware erratum. Skip instructions are
|
||||
@code{SBRS}, @code{SBRC}, @code{SBIS}, @code{SBIC} and @code{CPSE}.
|
||||
The second macro is only defined if @code{__AVR_HAVE_JMP_CALL__} is also
|
||||
set.
|
||||
|
||||
@item __AVR_SFR_OFFSET__=@var{offset}
|
||||
Instructions that can address I/O special function registers directly
|
||||
like @code{IN}, @code{OUT}, @code{SBI}, etc.@: may use a different
|
||||
address as if addressed by an instruction to access RAM like @code{LD}
|
||||
or @code{STS}. This offset depends on the device architecture and has
|
||||
to be subtracted from the RAM address in order to get the
|
||||
respective I/O@tie{}address.
|
||||
|
||||
@end table
|
||||
|
||||
@node Blackfin Options
|
||||
@subsection Blackfin Options
|
||||
@cindex Blackfin Options
|
||||
|
|
|
|||
|
|
@ -1768,14 +1768,8 @@ Constant integer 1
|
|||
@item G
|
||||
A floating point constant 0.0
|
||||
|
||||
@item R
|
||||
Integer constant in the range @minus{}6 @dots{} 5.
|
||||
|
||||
@item Q
|
||||
A memory address based on Y or Z pointer with displacement.
|
||||
|
||||
@item C04
|
||||
Constant integer 4
|
||||
@end table
|
||||
|
||||
@item Epiphany---@file{config/epiphany/constraints.md}
|
||||
|
|
|
|||
Loading…
Reference in New Issue