aarch64: Add backend support for expanding __builtin_memset
This patch implements aarch64 backend expansion for __builtin_memset. Most of the implementation is based on the expansion of __builtin_memcpy. We change the values of SET_RATIO and MOVE_RATIO for cases where we do not have to strictly align and where we can benefit from NEON instructions in the backend. gcc/ChangeLog: * config/aarch64/aarch64-protos.h (aarch64_expand_setmem): New declaration. * config/aarch64/aarch64.c (aarch64_gen_store_pair): Add case for E_V16QImode. (aarch64_set_one_block_and_progress_pointer): New helper for aarch64_expand_setmem. (aarch64_expand_setmem): Define the expansion for memset. * config/aarch64/aarch64.h (CLEAR_RATIO): Tweak to favor aarch64_expand_setmem when allowed and profitable. (SET_RATIO): Likewise. * config/aarch64/aarch64.md: Define pattern for setmemdi. gcc/testsuite/ChangeLog: * g++.dg/tree-ssa/pr90883.C: Remove xfail for aarch64. * gcc.dg/tree-prof/stringop-2.c: Add xfail for aarch64. * gcc.target/aarch64/memset-corner-cases.c: New test. * gcc.target/aarch64/memset-q-reg.c: New test.
This commit is contained in:
Sudakshina Das
parent
5e28fca09c
commit
54bbde550e
@ -510,6 +510,7 @@ bool aarch64_emit_approx_div (rtx, rtx, rtx);
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bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
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void aarch64_expand_call (rtx, rtx, rtx, bool);
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bool aarch64_expand_cpymem (rtx *);
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bool aarch64_expand_setmem (rtx *);
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bool aarch64_float_const_zero_rtx_p (rtx);
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bool aarch64_float_const_rtx_p (rtx);
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bool aarch64_function_arg_regno_p (unsigned);
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@ -7030,6 +7030,9 @@ aarch64_gen_store_pair (machine_mode mode, rtx mem1, rtx reg1, rtx mem2,
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case E_V4SImode:
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return gen_vec_store_pairv4siv4si (mem1, reg1, mem2, reg2);
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case E_V16QImode:
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return gen_vec_store_pairv16qiv16qi (mem1, reg1, mem2, reg2);
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default:
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gcc_unreachable ();
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}
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@ -21276,6 +21279,135 @@ aarch64_expand_cpymem (rtx *operands)
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return true;
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}
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/* Like aarch64_copy_one_block_and_progress_pointers, except for memset where
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SRC is a register we have created with the duplicated value to be set. */
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static void
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aarch64_set_one_block_and_progress_pointer (rtx src, rtx *dst,
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machine_mode mode)
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{
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/* If we are copying 128bits or 256bits, we can do that straight from
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the SIMD register we prepared. */
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if (known_eq (GET_MODE_BITSIZE (mode), 256))
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{
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mode = GET_MODE (src);
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/* "Cast" the *dst to the correct mode. */
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*dst = adjust_address (*dst, mode, 0);
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/* Emit the memset. */
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emit_insn (aarch64_gen_store_pair (mode, *dst, src,
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aarch64_progress_pointer (*dst), src));
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/* Move the pointers forward. */
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*dst = aarch64_move_pointer (*dst, 32);
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return;
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}
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if (known_eq (GET_MODE_BITSIZE (mode), 128))
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{
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/* "Cast" the *dst to the correct mode. */
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*dst = adjust_address (*dst, GET_MODE (src), 0);
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/* Emit the memset. */
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emit_move_insn (*dst, src);
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/* Move the pointers forward. */
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*dst = aarch64_move_pointer (*dst, 16);
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return;
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}
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/* For copying less, we have to extract the right amount from src. */
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rtx reg = lowpart_subreg (mode, src, GET_MODE (src));
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/* "Cast" the *dst to the correct mode. */
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*dst = adjust_address (*dst, mode, 0);
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/* Emit the memset. */
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emit_move_insn (*dst, reg);
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/* Move the pointer forward. */
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*dst = aarch64_progress_pointer (*dst);
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}
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/* Expand setmem, as if from a __builtin_memset. Return true if
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we succeed, otherwise return false. */
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bool
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aarch64_expand_setmem (rtx *operands)
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{
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int n, mode_bits;
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unsigned HOST_WIDE_INT len;
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rtx dst = operands[0];
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rtx val = operands[2], src;
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rtx base;
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machine_mode cur_mode = BLKmode, next_mode;
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/* We can't do anything smart if the amount to copy is not constant. */
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if (!CONST_INT_P (operands[1]))
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return false;
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bool speed_p = !optimize_function_for_size_p (cfun);
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/* Default the maximum to 256-bytes. */
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unsigned max_set_size = 256;
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/* In case we are optimizing for size or if the core does not
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want to use STP Q regs, lower the max_set_size. */
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max_set_size = (!speed_p
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|| (aarch64_tune_params.extra_tuning_flags
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& AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS))
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? max_set_size / 2 : max_set_size;
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len = INTVAL (operands[1]);
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/* Upper bound check. */
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if (len > max_set_size)
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return false;
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base = copy_to_mode_reg (Pmode, XEXP (dst, 0));
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dst = adjust_automodify_address (dst, VOIDmode, base, 0);
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/* Prepare the val using a DUP/MOVI v0.16B, val. */
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src = expand_vector_broadcast (V16QImode, val);
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src = force_reg (V16QImode, src);
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/* Convert len to bits to make the rest of the code simpler. */
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n = len * BITS_PER_UNIT;
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/* Maximum amount to copy in one go. We allow 256-bit chunks based on the
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AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS tuning parameter. setmem expand
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pattern is only turned on for TARGET_SIMD. */
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const int copy_limit = (speed_p
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&& (aarch64_tune_params.extra_tuning_flags
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& AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS))
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? GET_MODE_BITSIZE (TImode) : 256;
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while (n > 0)
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{
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/* Find the largest mode in which to do the copy without
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over writing. */
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opt_scalar_int_mode mode_iter;
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FOR_EACH_MODE_IN_CLASS (mode_iter, MODE_INT)
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if (GET_MODE_BITSIZE (mode_iter.require ()) <= MIN (n, copy_limit))
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cur_mode = mode_iter.require ();
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gcc_assert (cur_mode != BLKmode);
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mode_bits = GET_MODE_BITSIZE (cur_mode).to_constant ();
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aarch64_set_one_block_and_progress_pointer (src, &dst, cur_mode);
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n -= mode_bits;
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/* Do certain trailing copies as overlapping if it's going to be
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cheaper. i.e. less instructions to do so. For instance doing a 15
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byte copy it's more efficient to do two overlapping 8 byte copies than
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8 + 4 + 2 + 1. */
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if (n > 0 && n < copy_limit / 2)
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{
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next_mode = smallest_mode_for_size (n, MODE_INT);
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int n_bits = GET_MODE_BITSIZE (next_mode).to_constant ();
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gcc_assert (n_bits <= mode_bits);
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dst = aarch64_move_pointer (dst, (n - n_bits) / BITS_PER_UNIT);
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n = n_bits;
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}
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}
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return true;
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}
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/* Split a DImode store of a CONST_INT SRC to MEM DST as two
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SImode stores. Handle the case when the constant has identical
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bottom and top halves. This is beneficial when the two stores can be
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@ -1024,16 +1024,19 @@ typedef struct
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#define MOVE_RATIO(speed) \
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(!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
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/* For CLEAR_RATIO, when optimizing for size, give a better estimate
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of the length of a memset call, but use the default otherwise. */
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/* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when
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we would use more than 3 scalar instructions.
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Otherwise follow a sensible default: when optimizing for size, give a better
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estimate of the length of a memset call, but use the default otherwise. */
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#define CLEAR_RATIO(speed) \
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((speed) ? 15 : AARCH64_CALL_RATIO)
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(!STRICT_ALIGNMENT ? 4 : (speed) ? 15 : AARCH64_CALL_RATIO)
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/* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when
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optimizing for size adjust the ratio to account for the overhead of loading
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the constant. */
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/* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant. Without
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-mstrict-align, make decisions in "setmem". Otherwise follow a sensible
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default: when optimizing for size adjust the ratio to account for the
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overhead of loading the constant. */
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#define SET_RATIO(speed) \
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((speed) ? 15 : AARCH64_CALL_RATIO - 2)
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(!STRICT_ALIGNMENT ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2)
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/* Disable auto-increment in move_by_pieces et al. Use of auto-increment is
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rarely a good idea in straight-line code since it adds an extra address
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@ -1571,6 +1571,24 @@
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}
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)
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;; 0 is dst
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;; 1 is val
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;; 2 is size of copy in bytes
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;; 3 is alignment
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(define_expand "setmemdi"
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[(set (match_operand:BLK 0 "memory_operand") ;; Dest
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(match_operand:QI 2 "nonmemory_operand")) ;; Value
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(use (match_operand:DI 1 "immediate_operand")) ;; Length
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(match_operand 3 "immediate_operand")] ;; Align
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"TARGET_SIMD"
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{
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if (aarch64_expand_setmem (operands))
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DONE;
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FAIL;
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})
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;; Operands 1 and 3 are tied together by the final condition; so we allow
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;; fairly lax checking on the second memory operation.
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(define_insn "load_pair_sw_<SX:mode><SX2:mode>"
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@ -15,6 +15,6 @@
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// We want to match enough here to capture that we deleted an empty
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// constructor store
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// aarch64 and mips will expand to loop to clear because CLEAR_RATIO.
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// { dg-final { scan-tree-dump "Deleted redundant store: .*\.a = {}" "dse1" { xfail { aarch64-*-* mips*-*-* } } } }
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// mips will expand to loop to clear because CLEAR_RATIO.
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// { dg-final { scan-tree-dump "Deleted redundant store: .*\.a = {}" "dse1" { xfail { mips*-*-* } } } }
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@ -20,6 +20,6 @@ main()
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return 0;
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}
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/* autofdo doesn't support value profiling for now: */
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/* { dg-final-use-not-autofdo { scan-ipa-dump "Transformation done: single value 4 stringop" "profile"} } */
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/* { dg-final-use-not-autofdo { scan-ipa-dump "Transformation done: single value 4 stringop" "profile" { target { ! aarch64*-*-* } } } } */
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/* The versioned memset of size 4 should be optimized to an assignment.
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{ dg-final-use-not-autofdo { scan-tree-dump "MEM <\[a-z \]+> \\\[\\(void .\\)&a\\\] = 168430090" "optimized" } } */
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{ dg-final-use-not-autofdo { scan-tree-dump "MEM <\[a-z \]+> \\\[\\(void .\\)&a\\\] = 168430090" "optimized" { target { ! aarch64*-*-* } } } } */
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88
gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
Normal file
88
gcc/testsuite/gcc.target/aarch64/memset-corner-cases.c
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@ -0,0 +1,88 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-require-effective-target lp64 } */
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#include <stdint.h>
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/* One byte variable set should be scalar
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**set1byte:
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** strb w1, \[x0\]
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** ret
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*/
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void __attribute__((__noinline__))
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set1byte (int64_t *src, char c)
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{
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__builtin_memset (src, c, 1);
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}
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/* Special cases for setting 0. */
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/* 1-byte should be STRB with wzr
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**set0byte:
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** strb wzr, \[x0\]
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** ret
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*/
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void __attribute__((__noinline__))
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set0byte (int64_t *src)
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{
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__builtin_memset (src, 0, 1);
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}
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/* 35bytes would become 4 scalar instructions. So favour NEON.
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**set0neon:
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** movi v0.4s, 0
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** stp q0, q0, \[x0\]
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** str wzr, \[x0, 31\]
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** ret
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*/
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void __attribute__((__noinline__))
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set0neon (int64_t *src)
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{
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__builtin_memset (src, 0, 35);
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}
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/* 36bytes should be scalar however.
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**set0scalar:
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** stp xzr, xzr, \[x0\]
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** stp xzr, xzr, \[x0, 16\]
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** str wzr, \[x0, 32\]
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** ret
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*/
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void __attribute__((__noinline__))
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set0scalar (int64_t *src)
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{
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__builtin_memset (src, 0, 36);
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}
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/* 256-bytes expanded
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**set256byte:
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** dup v0.16b, w1
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** stp q0, q0, \[x0\]
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** stp q0, q0, \[x0, 32\]
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** stp q0, q0, \[x0, 64\]
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** stp q0, q0, \[x0, 96\]
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** stp q0, q0, \[x0, 128\]
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** stp q0, q0, \[x0, 160\]
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** stp q0, q0, \[x0, 192\]
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** stp q0, q0, \[x0, 224\]
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** ret
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*/
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void __attribute__((__noinline__))
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set256byte (int64_t *src, char c)
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{
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__builtin_memset (src, c, 256);
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}
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/* More than 256 bytes goes to memset
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**set257byte:
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** mov x2, 257
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** mov w1, 99
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** b memset
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*/
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void __attribute__((__noinline__))
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set257byte (int64_t *src)
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{
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__builtin_memset (src, 'c', 257);
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}
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/* { dg-final { check-function-bodies "**" "" "" } } */
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81
gcc/testsuite/gcc.target/aarch64/memset-q-reg.c
Normal file
81
gcc/testsuite/gcc.target/aarch64/memset-q-reg.c
Normal file
@ -0,0 +1,81 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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/* { dg-require-effective-target lp64 } */
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#include <stdint.h>
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/*
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**set128bits:
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** dup v0.16b, w1
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** str q0, \[x0\]
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** ret
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*/
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void __attribute__((__noinline__))
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set128bits (int64_t *src, char c)
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{
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__builtin_memset (src, c, 2*sizeof(int64_t));
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}
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/*
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**set128bitszero:
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** stp xzr, xzr, \[x0\]
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** ret
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*/
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void __attribute__((__noinline__))
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set128bitszero (int64_t *src)
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{
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__builtin_memset (src, 0, 2*sizeof(int64_t));
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}
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/*
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** set128bitsplus:
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** dup v0.16b, w1
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** str q0, \[x0\]
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** str q0, \[x0, 12\]
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** ret
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*/
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void __attribute__((__noinline__))
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set128bitsplus (int64_t *src, char c)
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{
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__builtin_memset (src, c, 7*sizeof(int32_t));
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}
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/*
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** set256bits:
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** movi v0.16b, 0x63
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** stp q0, q0, \[x0\]
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** ret
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*/
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void __attribute__((__noinline__))
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set256bits (int64_t *src)
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{
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__builtin_memset (src, 'c', 4*sizeof(int64_t));
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}
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/*
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**set256bitszero:
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** stp xzr, xzr, \[x0\]
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** stp xzr, xzr, \[x0, 16\]
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** ret
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*/
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void __attribute__((__noinline__))
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set256bitszero (int64_t *src)
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{
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__builtin_memset (src, 0, 4*sizeof(int64_t));
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}
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/*
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** set256bitsplus:
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** movi v0.16b, 0x63
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** stp q0, q0, \[x0\]
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** str q0, \[x0, 32\]
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** str d0, \[x0, 48\]
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** ret
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*/
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void __attribute__((__noinline__))
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set256bitsplus (int64_t *src)
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{
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__builtin_memset (src, 'c', 7*sizeof(int64_t));
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}
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/* { dg-final { check-function-bodies "**" "" "" } } */
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