From 54e73f88026e7c167232328e55d70551fa4aadda Mon Sep 17 00:00:00 2001 From: Andrew Stubbs Date: Fri, 9 Sep 2011 13:57:41 +0000 Subject: [PATCH] arm-cores.def (generic-armv7-a): New architecture. 2011-09-09 Andrew Stubbs gcc/ * config/arm/arm-cores.def (generic-armv7-a): New architecture. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. * config/arm/arm.c (arm_file_start): Output .arch directive when user passes -mcpu=generic-*. (arm_issue_rate): Add genericv7a support. * config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec. (ASM_CPU_SPEC): New define. * config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec). * config/arm/semi.h (ASM_SPEC): Likewise. * doc/invoke.texi (ARM Options): Document -mcpu=generic-* and -mtune=generic-*. From-SVN: r178731 --- gcc/ChangeLog | 15 +++++++++++++++ gcc/config/arm/arm-cores.def | 2 ++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 2 +- gcc/config/arm/arm.c | 3 +++ gcc/config/arm/arm.h | 5 +++++ gcc/config/arm/elf.h | 3 +-- gcc/config/arm/semi.h | 3 +-- gcc/doc/invoke.texi | 11 +++++++++++ 9 files changed, 42 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 87a114a1c7d..ce7c22c52ee 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2011-09-09 Andrew Stubbs + + * config/arm/arm-cores.def (generic-armv7-a): New architecture. + * config/arm/arm-tables.opt: Regenerate. + * config/arm/arm-tune.md: Regenerate. + * config/arm/arm.c (arm_file_start): Output .arch directive when + user passes -mcpu=generic-*. + (arm_issue_rate): Add genericv7a support. + * config/arm/arm.h (EXTRA_SPECS): Add asm_cpu_spec. + (ASM_CPU_SPEC): New define. + * config/arm/elf.h (ASM_SPEC): Use %(asm_cpu_spec). + * config/arm/semi.h (ASM_SPEC): Likewise. + * doc/invoke.texi (ARM Options): Document -mcpu=generic-* + and -mtune=generic-*. + 2011-09-09 Richard Guenther PR tree-optimization/50328 diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 11a6ad93b79..742b5e80ccd 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -124,6 +124,7 @@ ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e) ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e) ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, v6t2) ARM_CORE("arm1156t2f-s", arm1156t2fs, 6T2, FL_LDSCHED | FL_VFPV2, v6t2) +ARM_CORE("generic-armv7-a", genericv7a, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, cortex_a5) ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) @@ -135,3 +136,4 @@ ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, cortex) ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, cortex) ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, cortex) ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, cortex) + diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index 9b3ced651b5..d86e376b15d 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -231,6 +231,9 @@ Enum(processor_type) String(arm1156t2-s) Value(arm1156t2s) EnumValue Enum(processor_type) String(arm1156t2f-s) Value(arm1156t2fs) +EnumValue +Enum(processor_type) String(generic-armv7-a) Value(genericv7a) + EnumValue Enum(processor_type) String(cortex-a5) Value(cortexa5) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index bd1083315ca..4b439d03e42 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from arm-cores.def (define_attr "tune" - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0" + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,fa526,fa626,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,fa606te,fa626te,fmp626,fa726te,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,arm1156t2fs,genericv7a,cortexa5,cortexa8,cortexa9,cortexa15,cortexr4,cortexr4f,cortexr5,cortexm4,cortexm3,cortexm1,cortexm0" (const (symbol_ref "((enum attr_tune) arm_tune)"))) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index aaee3f40385..754956262a9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -22209,6 +22209,8 @@ arm_file_start (void) const char *fpu_name; if (arm_selected_arch) asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name); + else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0) + asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8); else asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_selected_cpu->name); @@ -23733,6 +23735,7 @@ arm_issue_rate (void) case cortexr4: case cortexr4f: case cortexr5: + case genericv7a: case cortexa5: case cortexa8: case cortexa9: diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 0a6e6f2ac50..1e8c29a1b1f 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -189,6 +189,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); Do not define this macro if it does not need to do anything. */ #define EXTRA_SPECS \ { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ + { "asm_cpu_spec", ASM_CPU_SPEC }, \ SUBTARGET_EXTRA_SPECS #ifndef SUBTARGET_EXTRA_SPECS @@ -2223,4 +2224,8 @@ extern int making_const_table; instruction. */ #define MAX_LDM_STM_OPS 4 +#define ASM_CPU_SPEC \ + " %{mcpu=generic-*:-march=%*;" \ + " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}" + #endif /* ! GCC_ARM_H */ diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 5ce3e690a39..e0a0aa06c18 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -56,8 +56,7 @@ #define ASM_SPEC "\ %{mbig-endian:-EB} \ %{mlittle-endian:-EL} \ -%{mcpu=*:-mcpu=%*} \ -%{march=*:-march=%*} \ +%(asm_cpu_spec) \ %{mapcs-*:-mapcs-%*} \ %(subtarget_asm_float_spec) \ %{mthumb-interwork:-mthumb-interwork} \ diff --git a/gcc/config/arm/semi.h b/gcc/config/arm/semi.h index ae8ddeae6e9..bbececef83f 100644 --- a/gcc/config/arm/semi.h +++ b/gcc/config/arm/semi.h @@ -61,8 +61,7 @@ #define ASM_SPEC "\ %{fpic|fpie: -k} %{fPIC|fPIE: -k} \ %{mbig-endian:-EB} \ -%{mcpu=*:-mcpu=%*} \ -%{march=*:-march=%*} \ +%(arm_cpu_spec) \ %{mapcs-float:-mfloat} \ %{mfloat-abi=*} %{mfpu=*} \ %{mthumb-interwork:-mthumb-interwork} \ diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3aa9611fa92..957d75ce964 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -10329,6 +10329,10 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}. +@option{-mcpu=generic-@var{arch}} is also permissible, and is +equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. +See @option{-mtune} for more information. + @item -mtune=@var{name} @opindex mtune This option is very similar to the @option{-mcpu=} option, except that @@ -10340,6 +10344,13 @@ will generate based on the CPU specified by a @option{-mcpu=} option. For some ARM implementations better performance can be obtained by using this option. +@option{-mtune=generic-@var{arch}} specifies that GCC should tune the +performance for a blend of processors within architecture @var{arch}. +The aim is to generate code that run well on the current most popular +processors, balancing between optimizations that benefit some CPUs in the +range, and avoiding performance pitfalls of other CPUs. The effects of +this option may change in future GCC versions as CPU models come and go. + @item -march=@var{name} @opindex march This specifies the name of the target ARM architecture. GCC uses this