[arm][2/2] Remove support for -march=armv3 and older
We deprecated architecture versions earlier than Armv4T in GCC 6 [1]. This patch removes support for architectures lower than Armv4. That is the -march values armv2, armv2a, armv3, armv3m are removed with this patch. I did not remove armv4 because it's a bit more involved code-wise and there has been some pushback on the implications for -mcpu=strongarm support. Removing armv3m and earlier though is pretty straightforward. This allows us to get rid of the armv3m and mode32 feature bits in arm-cpus.in as they can be assumed to be universally available. Consequently the mcpu values arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dm are now also removed. Bootstrapped and tested on arm-none-linux-gnueabihf and on arm-none-eabi with an aprofile multilib configuration (which builds quite a lot of library configurations). [1] https://gcc.gnu.org/gcc-6/changes.html#arm * config/arm/arm-cpus.in (armv3m, mode32): Delete features. (ARMv4): Update. (ARMv2, ARMv3, ARMv3m): Delete fgroups. (ARMv6m): Update. (armv2, armv2a, armv3, armv3m): Delete architectures. (arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi): Delete cpus. * config/arm/arm.md (maddsidi4): Remove check for arm_arch3m. (*mulsidi3adddi): Likewise. (mulsidi3): Likewise. (*mulsidi3_nov6): Likewise. (umulsidi3): Likewise. (umulsidi3_nov6): Likewise. (umaddsidi4): Likewise. (*umulsidi3adddi): Likewise. (smulsi3_highpart): Likewise. (*smulsi3_highpart_nov6): Likewise. (umulsi3_highpart): Likewise. (*umulsi3_highpart_nov6): Likewise. * config/arm/arm.h (arm_arch3m): Delete. * config/arm/arm.c (arm_arch3m): Delete. (arm_option_override_internal): Update armv3-related comment. (arm_configure_build_target): Delete use of isa_bit_mode32. (arm_option_reconfigure_globals): Delete set of arm_ach3m. (arm_rtx_costs_internal): Delete check of arm_arch3m. * config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m. (mulsa3): Likewise. (mulusa3): Likewise. * config/arm/arm-protos.h (arm_arch3m): Delete. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * config/arm/t-arm-elf (all_early_nofp): Delete mentions of deleted architectures. * gcc.target/arm/pr62554.c: Delete. * gcc.target/arm/pr69610-1.c: Likewise. * gcc.target/arm/pr69610-2.c: Likewise. From-SVN: r260363
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
c3f808d3f8
commit
5511d3fa7d
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@ -1,3 +1,41 @@
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2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm-cpus.in (armv3m, mode32): Delete features.
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(ARMv4): Update.
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(ARMv2, ARMv3, ARMv3m): Delete fgroups.
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(ARMv6m): Update.
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(armv2, armv2a, armv3, armv3m): Delete architectures.
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(arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620,
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arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720,
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arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi):
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Delete cpus.
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* config/arm/arm.md (maddsidi4): Remove check for arm_arch3m.
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(*mulsidi3adddi): Likewise.
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(mulsidi3): Likewise.
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(*mulsidi3_nov6): Likewise.
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(umulsidi3): Likewise.
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(umulsidi3_nov6): Likewise.
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(umaddsidi4): Likewise.
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(*umulsidi3adddi): Likewise.
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(smulsi3_highpart): Likewise.
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(*smulsi3_highpart_nov6): Likewise.
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(umulsi3_highpart): Likewise.
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(*umulsi3_highpart_nov6): Likewise.
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* config/arm/arm.h (arm_arch3m): Delete.
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* config/arm/arm.c (arm_arch3m): Delete.
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(arm_option_override_internal): Update armv3-related comment.
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(arm_configure_build_target): Delete use of isa_bit_mode32.
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(arm_option_reconfigure_globals): Delete set of arm_ach3m.
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(arm_rtx_costs_internal): Delete check of arm_arch3m.
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* config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m.
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(mulsa3): Likewise.
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(mulusa3): Likewise.
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* config/arm/arm-protos.h (arm_arch3m): Delete.
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* config/arm/arm-tables.opt: Regenerate.
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* config/arm/arm-tune.md: Likewise.
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* config/arm/t-arm-elf (all_early_nofp): Delete mentions of
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deleted architectures.
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2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/arm-cpus.in (armv5, armv5e): Delete features.
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@ -48,15 +48,9 @@
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# Features - general convention: all lower case.
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# Extended multiply
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define feature armv3m
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# 26-bit mode support
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define feature mode26
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# 32-bit mode support
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define feature mode32
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# Architecture rel 4
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define feature armv4
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@ -215,10 +209,7 @@ define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_I
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# -mfpu support.
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define fgroup ALL_FP fp16 ALL_FPU_INTERNAL
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define fgroup ARMv2 notm
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define fgroup ARMv3 ARMv2 mode32
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define fgroup ARMv3m ARMv3 armv3m
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define fgroup ARMv4 ARMv3m armv4
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define fgroup ARMv4 armv4 notm
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define fgroup ARMv4t ARMv4 thumb
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define fgroup ARMv5t ARMv4t armv5t
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define fgroup ARMv5te ARMv5t armv5te
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@ -232,7 +223,7 @@ define fgroup ARMv6zk ARMv6k
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define fgroup ARMv6t2 ARMv6 thumb2
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# This is suspect. ARMv6-m doesn't really pull in any useful features
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# from ARMv5* or ARMv6.
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define fgroup ARMv6m mode32 armv3m armv4 thumb armv5t armv5te armv6 be8
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define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8
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# This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
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# integer SIMD instructions that are in ARMv6T2. */
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define fgroup ARMv7 ARMv6m thumb2 armv7
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@ -279,34 +270,6 @@ define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd
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# end arch <name>
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#
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begin arch armv2
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tune for arm2
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tune flags CO_PROC NO_MODE32
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base 2
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isa ARMv2 mode26
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end arch armv2
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begin arch armv2a
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tune for arm2
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tune flags CO_PROC NO_MODE32
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base 2
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isa ARMv2 mode26
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end arch armv2a
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begin arch armv3
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tune for arm6
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tune flags CO_PROC
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base 3
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isa ARMv3 mode26
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end arch armv3
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begin arch armv3m
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tune for arm7m
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tune flags CO_PROC
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base 3M
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isa ARMv3m mode26
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end arch armv3m
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begin arch armv4
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tune for arm7tdmi
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tune flags CO_PROC
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@ -675,154 +638,6 @@ end arch iwmmxt2
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# option must similarly have a distinct feature set. Option aliases can be
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# added with the optalias statement
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# V2/V2A Architecture Processors
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begin cpu arm2
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tune flags CO_PROC NO_MODE32
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architecture armv2
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costs slowmul
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end cpu arm2
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begin cpu arm250
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tune flags CO_PROC NO_MODE32
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architecture armv2
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costs slowmul
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end cpu arm250
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begin cpu arm3
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tune flags CO_PROC NO_MODE32
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architecture armv2
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costs slowmul
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end cpu arm3
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# V3 Architecture Processors
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begin cpu arm6
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tune flags CO_PROC
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architecture armv3
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costs slowmul
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end cpu arm6
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begin cpu arm60
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tune flags CO_PROC
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architecture armv3
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costs slowmul
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end cpu arm60
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begin cpu arm600
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tune flags CO_PROC WBUF
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architecture armv3
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costs slowmul
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end cpu arm600
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begin cpu arm610
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tune flags WBUF
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architecture armv3
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costs slowmul
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end cpu arm610
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begin cpu arm620
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tune flags CO_PROC WBUF
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architecture armv3
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costs slowmul
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end cpu arm620
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begin cpu arm7
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tune flags CO_PROC
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architecture armv3
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costs slowmul
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end cpu arm7
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begin cpu arm7d
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tune flags CO_PROC
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architecture armv3
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costs slowmul
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end cpu arm7d
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begin cpu arm7di
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tune flags CO_PROC
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architecture armv3
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costs slowmul
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end cpu arm7di
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begin cpu arm70
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tune flags CO_PROC
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architecture armv3
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costs slowmul
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end cpu arm70
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begin cpu arm700
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tune flags CO_PROC WBUF
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architecture armv3
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costs slowmul
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end cpu arm700
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begin cpu arm700i
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tune flags CO_PROC WBUF
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architecture armv3
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costs slowmul
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end cpu arm700i
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begin cpu arm710
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tune flags WBUF
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architecture armv3
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costs slowmul
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end cpu arm710
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begin cpu arm720
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tune flags WBUF
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architecture armv3
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costs slowmul
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end cpu arm720
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begin cpu arm710c
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tune flags WBUF
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architecture armv3
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costs slowmul
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end cpu arm710c
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begin cpu arm7100
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tune flags WBUF
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architecture armv3
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costs slowmul
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end cpu arm7100
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begin cpu arm7500
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tune flags WBUF
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architecture armv3
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costs slowmul
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end cpu arm7500
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# Doesn't have an external co-proc, but does have embedded FPA
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# (the FPA part is no-longer supported).
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begin cpu arm7500fe
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tune flags CO_PROC WBUF
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architecture armv3
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costs slowmul
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end cpu arm7500fe
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# V3M Architecture Processors
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# arm7m doesn't exist on its own, but only with "D", (and "I"), but
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# those don't alter the code, so arm7m is sometimes used.
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begin cpu arm7m
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tune flags CO_PROC
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architecture armv3m
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costs fastmul
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end cpu arm7m
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begin cpu arm7dm
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tune flags CO_PROC
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architecture armv3m
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costs fastmul
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end cpu arm7dm
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begin cpu arm7dmi
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tune flags CO_PROC
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architecture armv3m
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costs fastmul
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end cpu arm7dmi
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# V4 Architecture Processors
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begin cpu arm8
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tune flags LDSCHED
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@ -137,7 +137,7 @@
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[(set (match_operand:SQ 0 "s_register_operand" "")
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(mult:SQ (match_operand:SQ 1 "s_register_operand" "")
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(match_operand:SQ 2 "s_register_operand" "")))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT"
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{
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rtx tmp1 = gen_reg_rtx (DImode);
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rtx tmp2 = gen_reg_rtx (SImode);
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@ -159,7 +159,7 @@
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[(set (match_operand:SA 0 "s_register_operand" "")
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(mult:SA (match_operand:SA 1 "s_register_operand" "")
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(match_operand:SA 2 "s_register_operand" "")))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT"
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{
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rtx tmp1 = gen_reg_rtx (DImode);
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rtx tmp2 = gen_reg_rtx (SImode);
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@ -178,7 +178,7 @@
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[(set (match_operand:USA 0 "s_register_operand" "")
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(mult:USA (match_operand:USA 1 "s_register_operand" "")
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(match_operand:USA 2 "s_register_operand" "")))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT"
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{
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rtx tmp1 = gen_reg_rtx (DImode);
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rtx tmp2 = gen_reg_rtx (SImode);
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@ -379,9 +379,6 @@ extern bool arm_is_constant_pool_ref (rtx);
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be used. */
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extern unsigned int tune_flags;
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/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
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extern int arm_arch3m;
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/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
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extern int arm_arch4;
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@ -24,75 +24,6 @@ Enum
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Name(processor_type) Type(enum processor_type)
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Known ARM CPUs (for use with the -mcpu= and -mtune= options):
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EnumValue
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Enum(processor_type) String(arm2) Value( TARGET_CPU_arm2)
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EnumValue
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Enum(processor_type) String(arm250) Value( TARGET_CPU_arm250)
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EnumValue
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Enum(processor_type) String(arm3) Value( TARGET_CPU_arm3)
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EnumValue
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Enum(processor_type) String(arm6) Value( TARGET_CPU_arm6)
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EnumValue
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Enum(processor_type) String(arm60) Value( TARGET_CPU_arm60)
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EnumValue
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Enum(processor_type) String(arm600) Value( TARGET_CPU_arm600)
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EnumValue
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Enum(processor_type) String(arm610) Value( TARGET_CPU_arm610)
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EnumValue
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Enum(processor_type) String(arm620) Value( TARGET_CPU_arm620)
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EnumValue
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Enum(processor_type) String(arm7) Value( TARGET_CPU_arm7)
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EnumValue
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Enum(processor_type) String(arm7d) Value( TARGET_CPU_arm7d)
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EnumValue
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Enum(processor_type) String(arm7di) Value( TARGET_CPU_arm7di)
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EnumValue
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Enum(processor_type) String(arm70) Value( TARGET_CPU_arm70)
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EnumValue
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Enum(processor_type) String(arm700) Value( TARGET_CPU_arm700)
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EnumValue
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Enum(processor_type) String(arm700i) Value( TARGET_CPU_arm700i)
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EnumValue
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Enum(processor_type) String(arm710) Value( TARGET_CPU_arm710)
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EnumValue
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Enum(processor_type) String(arm720) Value( TARGET_CPU_arm720)
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EnumValue
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Enum(processor_type) String(arm710c) Value( TARGET_CPU_arm710c)
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EnumValue
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Enum(processor_type) String(arm7100) Value( TARGET_CPU_arm7100)
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EnumValue
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Enum(processor_type) String(arm7500) Value( TARGET_CPU_arm7500)
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EnumValue
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Enum(processor_type) String(arm7500fe) Value( TARGET_CPU_arm7500fe)
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EnumValue
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Enum(processor_type) String(arm7m) Value( TARGET_CPU_arm7m)
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EnumValue
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Enum(processor_type) String(arm7dm) Value( TARGET_CPU_arm7dm)
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EnumValue
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Enum(processor_type) String(arm7dmi) Value( TARGET_CPU_arm7dmi)
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EnumValue
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Enum(processor_type) String(arm8) Value( TARGET_CPU_arm8)
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@ -365,106 +296,94 @@ Name(arm_arch) Type(int)
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Known ARM architectures (for use with the -march= option):
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EnumValue
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Enum(arm_arch) String(armv2) Value(0)
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Enum(arm_arch) String(armv4) Value(0)
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EnumValue
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Enum(arm_arch) String(armv2a) Value(1)
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Enum(arm_arch) String(armv4t) Value(1)
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EnumValue
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Enum(arm_arch) String(armv3) Value(2)
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Enum(arm_arch) String(armv5t) Value(2)
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EnumValue
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Enum(arm_arch) String(armv3m) Value(3)
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Enum(arm_arch) String(armv5te) Value(3)
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EnumValue
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Enum(arm_arch) String(armv4) Value(4)
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Enum(arm_arch) String(armv5tej) Value(4)
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EnumValue
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Enum(arm_arch) String(armv4t) Value(5)
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Enum(arm_arch) String(armv6) Value(5)
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EnumValue
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Enum(arm_arch) String(armv5t) Value(6)
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Enum(arm_arch) String(armv6j) Value(6)
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EnumValue
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Enum(arm_arch) String(armv5te) Value(7)
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Enum(arm_arch) String(armv6k) Value(7)
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EnumValue
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Enum(arm_arch) String(armv5tej) Value(8)
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Enum(arm_arch) String(armv6z) Value(8)
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EnumValue
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Enum(arm_arch) String(armv6) Value(9)
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Enum(arm_arch) String(armv6kz) Value(9)
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EnumValue
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Enum(arm_arch) String(armv6j) Value(10)
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Enum(arm_arch) String(armv6zk) Value(10)
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|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv6k) Value(11)
|
||||
Enum(arm_arch) String(armv6t2) Value(11)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv6z) Value(12)
|
||||
Enum(arm_arch) String(armv6-m) Value(12)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv6kz) Value(13)
|
||||
Enum(arm_arch) String(armv6s-m) Value(13)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv6zk) Value(14)
|
||||
Enum(arm_arch) String(armv7) Value(14)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv6t2) Value(15)
|
||||
Enum(arm_arch) String(armv7-a) Value(15)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv6-m) Value(16)
|
||||
Enum(arm_arch) String(armv7ve) Value(16)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv6s-m) Value(17)
|
||||
Enum(arm_arch) String(armv7-r) Value(17)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv7) Value(18)
|
||||
Enum(arm_arch) String(armv7-m) Value(18)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv7-a) Value(19)
|
||||
Enum(arm_arch) String(armv7e-m) Value(19)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv7ve) Value(20)
|
||||
Enum(arm_arch) String(armv8-a) Value(20)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv7-r) Value(21)
|
||||
Enum(arm_arch) String(armv8.1-a) Value(21)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv7-m) Value(22)
|
||||
Enum(arm_arch) String(armv8.2-a) Value(22)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv7e-m) Value(23)
|
||||
Enum(arm_arch) String(armv8.3-a) Value(23)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8-a) Value(24)
|
||||
Enum(arm_arch) String(armv8.4-a) Value(24)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8.1-a) Value(25)
|
||||
Enum(arm_arch) String(armv8-m.base) Value(25)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8.2-a) Value(26)
|
||||
Enum(arm_arch) String(armv8-m.main) Value(26)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8.3-a) Value(27)
|
||||
Enum(arm_arch) String(armv8-r) Value(27)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8.4-a) Value(28)
|
||||
Enum(arm_arch) String(iwmmxt) Value(28)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8-m.base) Value(29)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8-m.main) Value(30)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(armv8-r) Value(31)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(iwmmxt) Value(32)
|
||||
|
||||
EnumValue
|
||||
Enum(arm_arch) String(iwmmxt2) Value(33)
|
||||
Enum(arm_arch) String(iwmmxt2) Value(29)
|
||||
|
||||
Enum
|
||||
Name(arm_fpu) Type(enum fpu_type)
|
||||
|
|
|
|||
|
|
@ -21,42 +21,34 @@
|
|||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
(define_attr "tune"
|
||||
"arm2,arm250,arm3,
|
||||
arm6,arm60,arm600,
|
||||
arm610,arm620,arm7,
|
||||
arm7d,arm7di,arm70,
|
||||
arm700,arm700i,arm710,
|
||||
arm720,arm710c,arm7100,
|
||||
arm7500,arm7500fe,arm7m,
|
||||
arm7dm,arm7dmi,arm8,
|
||||
arm810,strongarm,strongarm110,
|
||||
strongarm1100,strongarm1110,fa526,
|
||||
fa626,arm7tdmi,arm7tdmis,
|
||||
arm710t,arm720t,arm740t,
|
||||
arm9,arm9tdmi,arm920,
|
||||
arm920t,arm922t,arm940t,
|
||||
ep9312,arm10tdmi,arm1020t,
|
||||
arm9e,arm946es,arm966es,
|
||||
arm968es,arm10e,arm1020e,
|
||||
arm1022e,xscale,iwmmxt,
|
||||
iwmmxt2,fa606te,fa626te,
|
||||
fmp626,fa726te,arm926ejs,
|
||||
arm1026ejs,arm1136js,arm1136jfs,
|
||||
arm1176jzs,arm1176jzfs,mpcorenovfp,
|
||||
mpcore,arm1156t2s,arm1156t2fs,
|
||||
cortexm1,cortexm0,cortexm0plus,
|
||||
cortexm1smallmultiply,cortexm0smallmultiply,cortexm0plussmallmultiply,
|
||||
genericv7a,cortexa5,cortexa7,
|
||||
cortexa8,cortexa9,cortexa12,
|
||||
cortexa15,cortexa17,cortexr4,
|
||||
cortexr4f,cortexr5,cortexr7,
|
||||
cortexr8,cortexm7,cortexm4,
|
||||
cortexm3,marvell_pj4,cortexa15cortexa7,
|
||||
cortexa17cortexa7,cortexa32,cortexa35,
|
||||
cortexa53,cortexa57,cortexa72,
|
||||
cortexa73,exynosm1,xgene1,
|
||||
cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
|
||||
cortexa73cortexa53,cortexa55,cortexa75,
|
||||
cortexa75cortexa55,cortexm23,cortexm33,
|
||||
cortexr52"
|
||||
"arm8,arm810,strongarm,
|
||||
strongarm110,strongarm1100,strongarm1110,
|
||||
fa526,fa626,arm7tdmi,
|
||||
arm7tdmis,arm710t,arm720t,
|
||||
arm740t,arm9,arm9tdmi,
|
||||
arm920,arm920t,arm922t,
|
||||
arm940t,ep9312,arm10tdmi,
|
||||
arm1020t,arm9e,arm946es,
|
||||
arm966es,arm968es,arm10e,
|
||||
arm1020e,arm1022e,xscale,
|
||||
iwmmxt,iwmmxt2,fa606te,
|
||||
fa626te,fmp626,fa726te,
|
||||
arm926ejs,arm1026ejs,arm1136js,
|
||||
arm1136jfs,arm1176jzs,arm1176jzfs,
|
||||
mpcorenovfp,mpcore,arm1156t2s,
|
||||
arm1156t2fs,cortexm1,cortexm0,
|
||||
cortexm0plus,cortexm1smallmultiply,cortexm0smallmultiply,
|
||||
cortexm0plussmallmultiply,genericv7a,cortexa5,
|
||||
cortexa7,cortexa8,cortexa9,
|
||||
cortexa12,cortexa15,cortexa17,
|
||||
cortexr4,cortexr4f,cortexr5,
|
||||
cortexr7,cortexr8,cortexm7,
|
||||
cortexm4,cortexm3,marvell_pj4,
|
||||
cortexa15cortexa7,cortexa17cortexa7,cortexa32,
|
||||
cortexa35,cortexa53,cortexa57,
|
||||
cortexa72,cortexa73,exynosm1,
|
||||
xgene1,cortexa57cortexa53,cortexa72cortexa53,
|
||||
cortexa73cortexa35,cortexa73cortexa53,cortexa55,
|
||||
cortexa75,cortexa75cortexa55,cortexm23,
|
||||
cortexm33,cortexr52"
|
||||
(const (symbol_ref "((enum attr_tune) arm_tune)")))
|
||||
|
|
|
|||
|
|
@ -850,9 +850,6 @@ struct arm_build_target arm_active_target;
|
|||
/* The following are used in the arm.md file as equivalents to bits
|
||||
in the above two flag variables. */
|
||||
|
||||
/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
|
||||
int arm_arch3m = 0;
|
||||
|
||||
/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
|
||||
int arm_arch4 = 0;
|
||||
|
||||
|
|
@ -3002,7 +2999,8 @@ arm_option_override_internal (struct gcc_options *opts,
|
|||
if (TARGET_INTERWORK && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb))
|
||||
{
|
||||
/* The default is to enable interworking, so this warning message would
|
||||
be confusing to users who have just compiled with, eg, -march=armv3. */
|
||||
be confusing to users who have just compiled with
|
||||
eg, -march=armv4. */
|
||||
/* warning (0, "ignoring -minterwork because target CPU does not support THUMB"); */
|
||||
opts->x_target_flags &= ~MASK_INTERWORK;
|
||||
}
|
||||
|
|
@ -3236,7 +3234,6 @@ arm_configure_build_target (struct arm_build_target *target,
|
|||
if (TARGET_INTERWORK || TARGET_THUMB)
|
||||
{
|
||||
bitmap_set_bit (sought_isa, isa_bit_thumb);
|
||||
bitmap_set_bit (sought_isa, isa_bit_mode32);
|
||||
|
||||
/* There are no ARM processors that support both APCS-26 and
|
||||
interworking. Therefore we forcibly remove MODE26 from
|
||||
|
|
@ -3636,7 +3633,6 @@ arm_option_reconfigure_globals (void)
|
|||
|
||||
/* Initialize boolean versions of the architectural flags, for use
|
||||
in the arm.md file. */
|
||||
arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_armv3m);
|
||||
arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv4);
|
||||
arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
|
||||
arm_arch5t = bitmap_bit_p (arm_active_target.isa, isa_bit_armv5t);
|
||||
|
|
@ -10005,8 +10001,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
|
|||
|
||||
if (mode == DImode)
|
||||
{
|
||||
if (arm_arch3m
|
||||
&& GET_CODE (XEXP (x, 0)) == MULT
|
||||
if (GET_CODE (XEXP (x, 0)) == MULT
|
||||
&& ((GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
|
||||
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == ZERO_EXTEND)
|
||||
|| (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
|
||||
|
|
@ -10204,11 +10199,10 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
|
|||
|
||||
if (mode == DImode)
|
||||
{
|
||||
if (arm_arch3m
|
||||
&& ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
|
||||
&& GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
|
||||
|| (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
|
||||
&& GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)))
|
||||
if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
|
||||
&& GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
|
||||
|| (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
|
||||
&& GET_CODE (XEXP (x, 1)) == SIGN_EXTEND))
|
||||
{
|
||||
if (speed_p)
|
||||
*cost += extra_cost->mult[1].extend;
|
||||
|
|
|
|||
|
|
@ -399,9 +399,6 @@ enum base_architecture
|
|||
/* The major revision number of the ARM Architecture implemented by the target. */
|
||||
extern enum base_architecture arm_base_arch;
|
||||
|
||||
/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
|
||||
extern int arm_arch3m;
|
||||
|
||||
/* Nonzero if this chip supports the ARM Architecture 4 extensions. */
|
||||
extern int arm_arch4;
|
||||
|
||||
|
|
|
|||
|
|
@ -1754,7 +1754,7 @@
|
|||
(sign_extend:DI (match_operand:SI 1 "s_register_operand" ""))
|
||||
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "")))
|
||||
(match_operand:DI 3 "s_register_operand" "")))]
|
||||
"TARGET_32BIT && arm_arch3m"
|
||||
"TARGET_32BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*mulsidi3adddi"
|
||||
|
|
@ -1764,7 +1764,7 @@
|
|||
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
|
||||
(sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
|
||||
(match_operand:DI 1 "s_register_operand" "0")))]
|
||||
"TARGET_32BIT && arm_arch3m && !arm_arch6"
|
||||
"TARGET_32BIT && !arm_arch6"
|
||||
"smlal%?\\t%Q0, %R0, %3, %2"
|
||||
[(set_attr "type" "smlal")
|
||||
(set_attr "predicable" "yes")]
|
||||
|
|
@ -1794,7 +1794,7 @@
|
|||
(mult:DI
|
||||
(sign_extend:DI (match_operand:SI 1 "s_register_operand" ""))
|
||||
(sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))))]
|
||||
"TARGET_32BIT && arm_arch3m"
|
||||
"TARGET_32BIT"
|
||||
""
|
||||
)
|
||||
|
||||
|
|
@ -1803,7 +1803,7 @@
|
|||
(mult:DI
|
||||
(sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
|
||||
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
|
||||
"TARGET_32BIT && arm_arch3m && !arm_arch6"
|
||||
"TARGET_32BIT && !arm_arch6"
|
||||
"smull%?\\t%Q0, %R0, %1, %2"
|
||||
[(set_attr "type" "smull")
|
||||
(set_attr "predicable" "yes")]
|
||||
|
|
@ -1825,7 +1825,7 @@
|
|||
(mult:DI
|
||||
(zero_extend:DI (match_operand:SI 1 "s_register_operand" ""))
|
||||
(zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))))]
|
||||
"TARGET_32BIT && arm_arch3m"
|
||||
"TARGET_32BIT"
|
||||
""
|
||||
)
|
||||
|
||||
|
|
@ -1834,7 +1834,7 @@
|
|||
(mult:DI
|
||||
(zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
|
||||
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
|
||||
"TARGET_32BIT && arm_arch3m && !arm_arch6"
|
||||
"TARGET_32BIT && !arm_arch6"
|
||||
"umull%?\\t%Q0, %R0, %1, %2"
|
||||
[(set_attr "type" "umull")
|
||||
(set_attr "predicable" "yes")]
|
||||
|
|
@ -1858,7 +1858,7 @@
|
|||
(zero_extend:DI (match_operand:SI 1 "s_register_operand" ""))
|
||||
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "")))
|
||||
(match_operand:DI 3 "s_register_operand" "")))]
|
||||
"TARGET_32BIT && arm_arch3m"
|
||||
"TARGET_32BIT"
|
||||
"")
|
||||
|
||||
(define_insn "*umulsidi3adddi"
|
||||
|
|
@ -1868,7 +1868,7 @@
|
|||
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
|
||||
(zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
|
||||
(match_operand:DI 1 "s_register_operand" "0")))]
|
||||
"TARGET_32BIT && arm_arch3m && !arm_arch6"
|
||||
"TARGET_32BIT && !arm_arch6"
|
||||
"umlal%?\\t%Q0, %R0, %3, %2"
|
||||
[(set_attr "type" "umlal")
|
||||
(set_attr "predicable" "yes")]
|
||||
|
|
@ -1897,7 +1897,7 @@
|
|||
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 ""))])]
|
||||
"TARGET_32BIT && arm_arch3m"
|
||||
"TARGET_32BIT"
|
||||
""
|
||||
)
|
||||
|
||||
|
|
@ -1910,7 +1910,7 @@
|
|||
(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 "=&r,&r"))]
|
||||
"TARGET_32BIT && arm_arch3m && !arm_arch6"
|
||||
"TARGET_32BIT && !arm_arch6"
|
||||
"smull%?\\t%3, %0, %2, %1"
|
||||
[(set_attr "type" "smull")
|
||||
(set_attr "predicable" "yes")]
|
||||
|
|
@ -1941,7 +1941,7 @@
|
|||
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 ""))])]
|
||||
"TARGET_32BIT && arm_arch3m"
|
||||
"TARGET_32BIT"
|
||||
""
|
||||
)
|
||||
|
||||
|
|
@ -1954,7 +1954,7 @@
|
|||
(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
|
||||
(const_int 32))))
|
||||
(clobber (match_scratch:SI 3 "=&r,&r"))]
|
||||
"TARGET_32BIT && arm_arch3m && !arm_arch6"
|
||||
"TARGET_32BIT && !arm_arch6"
|
||||
"umull%?\\t%3, %0, %2, %1"
|
||||
[(set_attr "type" "umull")
|
||||
(set_attr "predicable" "yes")]
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ v7ve_fps := vfpv3-d16 vfpv3 vfpv3-d16-fp16 vfpv3-fp16 vfpv4 neon \
|
|||
v8_fps := simd fp16 crypto fp16+crypto dotprod fp16fml
|
||||
|
||||
# We don't do anything special with these. Pre-v4t probably doesn't work.
|
||||
all_early_nofp := armv2 armv2a armv3 armv3m armv4 armv4t armv5t
|
||||
all_early_nofp := armv4 armv4t armv5t
|
||||
|
||||
all_early_arch := armv5tej armv6 armv6j armv6k armv6z armv6kz \
|
||||
armv6zk armv6t2 iwmmxt iwmmxt2
|
||||
|
|
|
|||
|
|
@ -15904,9 +15904,7 @@ Permissible names are:
|
|||
@samp{iwmmxt} and @samp{iwmmxt2}.
|
||||
|
||||
Additionally, the following architectures, which lack support for the
|
||||
Thumb execution state, are recognized but support is deprecated:
|
||||
@samp{armv2}, @samp{armv2a}, @samp{armv3}, @samp{armv3m},
|
||||
@samp{armv4}.
|
||||
Thumb execution state, are recognized but support is deprecated: @samp{armv4}.
|
||||
|
||||
Many of the architectures support extensions. These can be added by
|
||||
appending @samp{+@var{extension}} to the architecture name. Extension
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
|
||||
|
||||
* gcc.target/arm/pr62554.c: Delete.
|
||||
* gcc.target/arm/pr69610-1.c: Likewise.
|
||||
* gcc.target/arm/pr69610-2.c: Likewise.
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2018-05-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* gcc.target/arm/pr40887.c: Update comment.
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|
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Reference in New Issue